Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16588 Discussions

TCL/python script to check single/multiple verilog file(s) for improper or incorrect connections

Pack_of_lone_wolves
1,061 Views

Is it feasible to write a TCL/py script which will check single/multiple verilog file(s) for improper or incorrect connections:

  1. A signal var (usually input) attached to a module instance inside a container module to a (valid) port (of instance) which has not been declared either as wire or reg in the container module.
  2. A signal var (usually output) which is connected to a module instance, but it is not driven by or connected to (by any of the instance module's output) either as a reg or wire.
  3. Incorrectly interchanging wires to instances.
  4. There may be more cases of connectivity errors introduced due to programmer's mistake, but right now these are the ones that come to my mind.

I have seen some times that the synthesis engine detects such issues and starts optimizing the design for any regs or nets which are not connected, it will start reducing/eliminating them.

 

These kind of mistakes are very frequent, where people writing HDL codes sometimes miss making the proper connections and/or make incorrect connections, which results in the design not working the way it should have worked. 

 

Is there any utility in the Quartus Prime SW which can check for such mistakes or is it possible to write a user defined script which can be run every time before compiling the design?

0 Kudos
1 Solution
ShengN_Intel
Employee
1,009 Views

Hi,


Probably can check those mistakes through synthesis tool error and warnings.

Like 1. A signal var (usually input) attached to a module instance inside a container module to a (valid) port (of instance) which has not been declared either as wire or reg in the container module.

The tool probably will throw out error like object "" on left-hand side of assignment must have a variable data type 

Like 2. A signal var (usually output) which is connected to a module instance, but it is not driven by or connected to (by any of the instance module's output) either as a reg or wire.

The tool will throw out warning in synthesis report (.syn.rpt) under section Top Causes of Logic Optimized Away During Sweep like Output port "" in instance "" of entity "" does not have a driver. Connecting to the default value "gnd"


As for 3. Incorrectly interchanging wires to instances., easier way is to check through rtl simulation by writing some testing senario in testbench.


Thanks,

Best regards,

Sheng




View solution in original post

10 Replies
ShengN_Intel
Employee
1,010 Views

Hi,


Probably can check those mistakes through synthesis tool error and warnings.

Like 1. A signal var (usually input) attached to a module instance inside a container module to a (valid) port (of instance) which has not been declared either as wire or reg in the container module.

The tool probably will throw out error like object "" on left-hand side of assignment must have a variable data type 

Like 2. A signal var (usually output) which is connected to a module instance, but it is not driven by or connected to (by any of the instance module's output) either as a reg or wire.

The tool will throw out warning in synthesis report (.syn.rpt) under section Top Causes of Logic Optimized Away During Sweep like Output port "" in instance "" of entity "" does not have a driver. Connecting to the default value "gnd"


As for 3. Incorrectly interchanging wires to instances., easier way is to check through rtl simulation by writing some testing senario in testbench.


Thanks,

Best regards,

Sheng




Pack_of_lone_wolves
968 Views

Thank You for answering my question, it helps, turns out that I found out about this phenomenon exactly through the synthesis report, but wondered if there is any other way to automatically make sure that things like that don't happen or get detected and notified? Only when I had a look at them, I sensed something unusual but I'm not sure if I saw any specific warning out of the sea of warning messages.

0 Kudos
sstrell
Honored Contributor III
964 Views

@Pack_of_lone_wolves wrote:

Thank You for answering my question, it helps, turns out that I found out about this phenomenon exactly through the synthesis report, but wondered if there is any other way to automatically make sure that things like that don't happen or get detected and notified? Only when I had a look at them, I sensed something unusual but I'm not sure if I saw any specific warning out of the sea of warning messages.


You can run full synthesis (Analysis & Synthesis) but this takes longer than Analysis & Elaboration.  And you can filter the messages output by the compiler to focus on just errors or warnings/critical warnings with the checkboxes at the top of the Messages window.

0 Kudos
sstrell
Honored Contributor III
988 Views

Yeah, just run Analysis & Elaboration instead of full synthesis in Quartus.  This will catch errors like this before any synthesis is performed.

Pack_of_lone_wolves
970 Views

Do you mean "Analysis and Synthesis" instead of "Fitter"? If it catches the errors, do I need to look at the reports as suggested by @ShengN_Intel ?

0 Kudos
ShengN_Intel
Employee
946 Views

Hi,


Beside the Start Analysis & Synthesis, got the Start Analysis & Elaboration. Both the error or warning, you may check at the bottom message panel or through the syn report.


Thanks,

Best Regards,

Sheng


Pack_of_lone_wolves
866 Views

Is that (Analysis and Elaboration) option available for Quartus Prime Pro software? asking as I have not spot it on the home tab.

0 Kudos
sstrell
Honored Contributor III
853 Views
Processing menu -> Start -> Start Analysis & Elaboration
ShengN_Intel
Employee
799 Views

Hi,


Do you have any further update or concern?


Thanks,

Best Regards,

Sheng


Pack_of_lone_wolves
766 Views

No, you can close this thread. Thank You for your guidance and time!

0 Kudos
Reply