UART IP core

[Altera_Forum]

Hi everyone! 

 I am trying to make some tests with an FPGA and while trying to add an UART to my design using the Quartus II v13.0 SP1 and the Megawizard plug-in I realised that there is no UART available there but it is available from Qsys tool.    My questions are about add this IP from a Qsys system.     1) I don't want to add a NIOS II processor, so I want to controle this IP using the signals (its ports) and not the Avalon MMS function (by registers). I want neither to use the IRQ line. I am not sure wether this is possible or not.    2) Looking for the VHDL template to instatiate the Qsys system I didn't find a .vhd file. How should I instatiate this in my Quartus II design?

[Altera_Forum]

You may add the uart ip into the Qsys system; then, you expose the control port instead of connecting it to an avalon master. 

If you don't need to stick with the altera uart ip you can even use an open source core: there's a plenty of them available