I try to simulate Generic parity detector example in the book Circuit Design with VHDL. (Velnei A. Pedroni). But, simulation waveform editor gives an error. My synthesis editor is Quartus 2 web edition. My os is Wİndows 8. 64 bit. The error is below, please anyone help meERROR: If I run simulation functional simulation: # ** Warning: (vlib-34) Library already exists at "work".# # Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013# -- Compiling module parity_dec # # Top level modules:# parity_dec# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013# -- Compiling module parity_dec_vlg_sample_tst# ** Error: Waveform9.vwf.vt(31): near ",": syntax error, unexpected ',' # ** Error: c:/altera/14.0/modelsim_ase/win32aloem/vlog failed. # Executing ONERROR command at macro ./parity.do line 4.
Hi,Have you run analysis & synthesis without any error? Can you elaborate on steps you have followed? I was able to run the simulation without any error. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Apparently the Modelsim front end reading the vwf file has problems with the syntax. May be due to an unusual signal name or an some other unsupported entry.You can: - open Waveform9.vwf.vt with a text editor and try to understand which original waveform editor entry migh show at line 31 and what's probably wrong with it. - try to run the simulation with an old Quartus version supporting the classic Quartus simulator - set up a Modelsim test bench for the simulation
For what it's worth, the VWF simulator gave me only flatline outputs in the generated VWF file, even on the simplest possible logic. (I saw no error message appear, though). This persisted from the first time I tried it after installing Quartus Prime 18.0 Lite. However, once I restored defaults as indicated in the prior posting, simulation started working properly.