Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16638 Discussions

Use of permanently enabled tristate buffer

Altera_Forum
Honored Contributor II
‎11-27-2008 02:14 PM
1,060 Views

Hi, 

On an existing design, I've seen a gated clock output being buffered at the pin with a 'SOFT' buffer in series with a permanently enabled tristate buffer. As I am not familar with this arrangement, can anybody explain why this might have been tackled in this manner? 

 

Thanks, 

Tim 

 

Note: The 'soft' and 'tristate' buffers in this design appear on a schematic entry diagram driving an output pin.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎11-27-2008 05:58 PM
279 Views

You get a permanently enabled tristate buffer, if a signal is defined as inout but only used as output. Quartus isues a warning to remind you, that something may have been forgotten in the design definition.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.