VHDL-2008 support for unconstrained arrays in records

Altera_Forum · ‎10-01-2013

Quartus II does not support unconstrained arrays in records, which would be useful to define a complex-valued data type for signed values, eg.,


-- A complex-valued signed number
type complex_signed_t is record
    re : signed;
    im : signed;
end record;

or for fixed-point values (using the sfixed VHDL package). The attached example shows that this feature is supported by Modelsim (including Modelsim-ASE).

I filed a Service Request with Altera to ask for this feature, and the response (today) was

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Our software engineering plan to add this feature support in 14.1

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I figured that since this feature might be interesting to others, I'd post this to the forum.

I have no idea when 14.1 will be released :)

Cheers,

Dave

Altera_Forum · ‎10-01-2013

I wouldnt be surprised if this gets pushed back again. Altera have been rather half hearted at adding 2008 features. At least the support is better than Xilinx!

2008 has been around for 4 years now! Still no official support for the fixed point packages!

Altera_Forum · ‎10-10-2013

both vendors seem to be focusing on high level synthesis instead of complete System Verilog and VHDL 2008 support

Altera_Forum · ‎10-11-2013

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both vendors seem to be focusing on high level synthesis instead of complete System Verilog and VHDL 2008 support

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Yup - all about expanding the market, rather than improving the current one.

Altera_Forum · ‎10-04-2014

I just found that records with unconstrained elements is not supported in Quartus 14.0...I had high hopes since arrays of unconstraned elements is supported.

In VHDL-2008 record elements can be constrained while defining signals of the type.

Hopefully this will be supported soon...


  TYPE record_type_t IS RECORD
    data   : STD_LOGIC_VECTOR;
    enable : STD_LOGIC;
  END RECORD;
  SIGNAL a_record : record_type_t(data(7 DOWNTO 0));
  SIGNAL b_record : record_type_t(data(6 DOWNTO 0));

Altera_Forum · ‎10-05-2014

If you want it supported, I suggest raising a mysupport ticket.

PTorr1 · ‎01-17-2019

It does not seem to be supported on Quartus 18.1

It is supported on Modelsim: "ALTERA STARTER EDITION vsim 10.5b Simulator 2016.10 Oct 5 2016", which is the one distributed with Quartus 18.1

When trying to use the following record in a file:

    type t_avst_tosink is record
        data  : std_logic_vector;
        sop   : std_logic;
        eop   : std_logic;
        valid : std_logic;
    end record t_avst_tosink;

I get the following error in quartus:

Error (10482): VHDL error at example.vhd(80): object "data" is used but not declared File: /home/user/example.vhd Line: 80
Error (10411): VHDL Type Conversion error at example.vhd(80): can't determine type of object or expression near text or symbol "t_avst_tosink" File: /home/user/example.vhd Line: 80

PTorr1 · ‎01-18-2019

Just as an update, after contacting the support team, this feature is not available in the Standard Version, it is in Pro:

"...

I have consulted the case with engineers and I can confirm that Quartus Standard does not support unconstrained arrays inside of a VHDL.

As I know there is not any plan to provide this functionality.

My recommendation is to use Quartus Pro.

Best regards,

Intel PSG Support ..."