VHDL "others" problem

Altera_Forum · ‎03-22-2009

Hi, this is my first post on this forum.

I have a problem when compiling this code with Quartus II 8.0 web edition:

type tag_array is array (0 to 255) of std_logic_vector(7 to 0); -- tipo per il campo TAG

[...]

signal TAG :tag_array;

TAG<= (others=>'0');

[...]

The compilation fails on the last line (TAG<= (others=>'0');)

I have found this code on internet and and I try to understand

because it doesn't work.

Altera_Forum · ‎03-22-2009

Hi,

you should write

TAG<= (others => (others=>'0'));

or

TAG<= (others=>"00000000");

since it is two _D signal

edit:

you got another mistake here:

type tag_array is array (0 to 255) of std_logic_vector(7 to 0);

Altera_Forum · ‎03-22-2009

Ok, it now work!

Thanks! :-)