Variables are showing abnormal contents in Time simulation

[Altera_Forum]

I am new to VHDL and using Quartus II to synthesis my program. My functional simulation is ok but when I am doing time simulation the values of variables : queue_length and x10_queue are showing some values that do not follow my code. 

 ---------------------------------------------------------------------------------------------------------------   if (clk'event and clk='1') then  if (x10_packet_in/=0) and (x10_packet_in/=prev_packet) and (queue_length/=10) then  x10_queue(rear):=x10_packet_in;  prev_packet:=x10_packet_in;  rear:=rear+1;  queue_length:=queue_length+1;  if rear = 10 then  rear:=0;  end if;  end if;    ----------------------------------------------------------------------------------------------------------------   Values of queue_length variable should be incremented by 1 each time. But its sequence is like 0-1-2-3-2-7-3-8-5-10 …… .Why it is behaving like this??   queue_length and rear should be same but its showing difference.     And sometimes values of x10_queue variable is becoming 0 after inserting a value. I attached the vwf file here.    Can any one explain this for me? I don’t know what mistake I am doing here. Functional simulation is quite ok. Please help , I am totally stuck here. No way to proceed.   Thanks in advanced.   Raisul

[Altera_Forum]

Quartus creates a vwf file with a default grid of 10 ns. I'm almost sure your Clock period is 10 ns. and your design is slower. 

 Look for the classing timing analizer or time quest and look for your max. operating frequency.  Try with a higher clock period

[Altera_Forum]

Also make sure you are using the right math packages (unsigned vs. signed). Sounds like the previous poster's comment was most likely though. Make sure your clock is going at the period that you mean it to be going at.

[Altera_Forum]

--- Quote Start ---  Quartus creates a vwf file with a default grid of 10 ns. I'm almost sure your Clock period is 10 ns. and your design is slower.   Look for the classing timing analizer or time quest and look for your max. operating frequency.   Try with a higher clock period  --- Quote End ---     Thanks a lot.   Yas.You are right, The problem was for higher clock frequency. There was also some problem for some signals setup time and hold time.   Problem solved ! ! !

[Altera_Forum]

--- Quote Start ---  Also make sure you are using the right math packages (unsigned vs. signed). Sounds like the previous poster's comment was most likely though. Make sure your clock is going at the period that you mean it to be going at.  --- Quote End ---       Thanks.   The problem was not for incorrect usage of the variable.Its for clock higher frequency , incorrect hold time and setup time of some signals.   One should care about the usage of variables in VHDL. Thanks for remind me about this.