Warning Msg in system console "could not resgister IService packet"

[DeadEnd]

Hi, I have a question.

In system console, there were 2 kind of warning messages in Messages field.

Warning messages are as below.

   1. Could ot register IService packet

   2. A service named 'packet' is already registered.

Do you let me know why did warning messages occurred?

Alos when I ran .tcl file in system console, there was an error message "Driver is not an open data_pattern_generator service"

Is this error message related to above warning message?

[ShengN_Intel · Accepted solution]

Hi,

Those warnings probably are not the root cause. I encountered same warnings as well but don't have problem at performing system console check image below.

I follow the tcl script (main.tcl) attached below for your reference in this example design https://www.intel.com/content/www/us/en/docs/programmable/683758/21-3-19-2-0/hardware-test-for-system-console-control.html

Make sure you have correct $master_index. May be can try to run simple commands below to check whether the problem still exist:

set master_path [ lindex [ get_service_paths master ] $master_index ]

open_service master $master_path

master_write_32 $master_path

Thanks,

Best Regards,

Sheng

[DeadEnd]

Thank you for your help,

I have done HW_Test as you mentioned but.... result was failed...

So, what could be causing the HW issue? could you let me know how can I fix this error?

or do you need more information about HW?

Again, thank you so much for your help.

Below is the log in Tcl console. 

======================================================================================

% get_service_paths master
{/devices/5SGXEA7H(1|2|2ES|3|3ES)|..@1#USB-0/(link)/JTAG/(110:132 v1 #0)/phy_0/master}

{/devices/5SGXEA7H(1|2|2ES|3|3ES)|..@1#USB-0/(link)/JTAG/(70:34 v3 #0)/nios2_0}

% source main.tcl
Info : {/devices/5SGXEA7H(1|2|2ES|3|3ES)|..@1#USB-0/(link)/JTAG/(110:132 v1 #0)/phy_0/master} {/devices/5SGXEA7H(1|2|2ES|3|3ES)|..@1#USB-0/(link)/JTAG/(70:34 v3 #0)/nios2_0}
master_list_length = 2

--- Initialization (Check master path) ---
master_list_length = 2
Info : Master path=/devices/5SGXEA7H(1|2|2ES|3|3ES)|..@1#USB-0/(link)/JTAG/(70:34 v3 #0)/nios2_0 and Index= 1

% start_basic_test
---Read Initial Status----
master_list_length = 2
PIO Status = 0x10c00326
master_list_length = 2
Reset done!
master_list_length = 2
Enabled loopback done
master_list_length = 2
Waiting for reset seq active low...
Reset seq active low
Link and frame reset held
Waiting for reset seq active low...
Reset seq active low
master_list_length = 2
Setting tx_test & rx_test registers...
Set test mode to PRBS test pattern
Waiting for reset seq active low...
Reset seq active low
Link and frame reset released
Waiting for reset seq active low...
Reset seq active low
master_list_length = 2
Error status registers cleared
TX Error Status= 0x000000ff
RX Error0 Status= 0x000000ff
RX Error1 Status= 0x000003ff
master_list_length = 2
Pulse sysref done!
tx_status: 0x000000ff
rx_status1: 0x000000ff
rx_status2: 0x000003ff
rx_status1_masked = 0x1
f_value: 3
k_value: 1
rbd_count: 254
offset = 252
master_list_length = 2
Reset done!
master_list_length = 2
Waiting for reset seq active low...
Reset seq active low
Link and frame reset held
Waiting for reset seq active low...
Reset seq active low
master_list_length = 2
Setting tx_test & rx_test registers...
Set test mode to PRBS test pattern
master_list_length = 2
New RBD offset = 254
Waiting for reset seq active low...
Reset seq active low
Link and frame reset released
Waiting for reset seq active low...
Reset seq active low
master_list_length = 2
Error status registers cleared
TX Error Status= 0x000000ff
RX Error0 Status= 0x000000ff
RX Error1 Status= 0x000003ff
master_list_length = 2
Pulse sysref done!
tx_status: 0x000000ff
rx_status1: 0x000000ff
rx_status2: 0x000003ff
rx_status1_masked = 0x1
master_list_length = 2
Info : Master path=/devices/5SGXEA7H(1|2|2ES|3|3ES)|..@1#USB-0/(link)/JTAG/(70:34 v3 #0)/nios2_0
Status: 0x26 (Masked value)
Info: Bit 0 - Core PLL Locked
Info: Bit 1 - TX XCVR Ready
Info: Bit 2 - RX XCVR Ready
Info: Bit 3 - Patchk Data Error
Info: Bit 4 - Tx Link Error
Info: Bit 5 - Rx Link Error
TX Status0: 0x4 (Masked value)
Info: Bit 0 - SYNC_N
Info: Bit {2:1} - Data Link Layer (DLL)
- 00: Code Group Synchronization (CGS)
- 01: Initial Lane Alignment Sequence (ILAS)
- 10: User Data Mode
- 11: D21.5 test mode
RX Status0: 0x0 (Masked value)
Info: Bit 0 - SYNC_N
HW_TEST : FAIL
master_list_length = 2
Read Error Status Register
TX Error Status = 0x000000ff
RX Error0 Status = 0x000000ff
RX Error1 Status = 0x000003ff

%

[ShengN_Intel]

Hi,

Glad to hear that the system console problem had been resolved. As for HW_TEST : FAIL problem, probably have to open a new thread in this forum https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/bd-p/fpga-soc-cpld-boards-kits targeted on related ip hardware configuration.

Thanks,

Best Regards,

Sheng

[DeadEnd]

Thank you for your help.

I'll ask hw issue solution to HW community.

Have a good day!