Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16971 Discussions

Xcelium Simulation of Agile5 design FATAL when entering Simulation?

ThomasTessier
New Contributor I
607 Views

I have a very large DUT mixed-signal environment that I am integrating into with a new Agile5 FPGA design. I have this environment working with the Arria5 in previous generations. So this is entirely focused on the Agile5.

This appears to be focused on the new "tennm" libraries in some why but I cannot seem to figure out what Xcelium switch (or combination) I am missing.

Below is a screen shot of the FATAL that is happening in simulation. I am unsure what is meant by the "-SV_LIB" switch and the shared object?

Any assistance would be welcome.

TomT...

 

ThomasTessier_0-1722522095485.png

 

Labels (1)
0 Kudos
3 Replies
ThomasTessier
New Contributor I
577 Views

Still not solved, but I did run the canned xcelium_setup.sh created in our Platform Designer block in the QSYS_DIR/sim/xcelium_setup.sh. When running this script I modified it to show me the commands which are being executed for xmelab and xmsim. I do not see the switch "-sv_lib" set in this conditions and the simulation runs to completion.

So this is the actual FPGA design which is not instantiated with our Testbench and DUT. The one difference that I notice is that there is a "libdpi.so" in this directory so it is just picking up this default name and location. Our environment is a little more complex because we also do incremental compile for the design as the various DUT pieces take quite some time.

So I am still a little baffled given that I am able to run the UNIT simulation created by QUARTUS for our FPGA and it runs fine with any additional switches.

Any thoughts?

TomT...

 

 

0 Kudos
TingJiangT_Intel
Employee
454 Views

Hi there, you may have missing some libraries or flags, please check this link and get more information:

https://www.intel.com/content/www/us/en/docs/programmable/813752/24-1/cadence-cadence-xcelium-simulation-steps.html


0 Kudos
ThomasTessier
New Contributor I
380 Views

I was able to resolve this once I understood there was a C program that needed to be compiled to use the "tennm" libraries.  This was buried in the ncsim_setup.sh script and wasn't mentioned in the documentation that it was necessary.  This see program generated the default dpilib.so files when compiled.  As long as this file was available to the simulation it works.  So my flow now includes compiling this program in my simulation directory.

 

Thanks,

TomT....

0 Kudos
Reply