06-16-2016 09:50 AM
Hi,My toplevel design is in system verilog, I import a VHDL package with record type, quartus errors with "Error (10161): Verilog HDL error at dummy_sysver.sv(3): object "dummy_vhd_pkg" is not declared" To simulate I used modelsim -mixedsvvh and I don't have any problem simulating. however when I try compiling the design with quartus I get the error above. I made sure all signal are plain lowercase, I've also tried compiling vhdl in a different library. I have also tried creating a system verilog package with packed structure mimicking the vhdl records, compilation goes a bit further, but then I get error indicating the vhdl record output don't exist. anything else I could try ? for reference : I am using Quartus 14.1 ---- my vhdl package:---- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; package dummy_vhd_pkg is type dummy_vhd_type1 is record dummy_vhd_type1_sig1 : std_logic; -- dummy_vhd_type1_sig2 : std_logic; -- end record; constant dummy_vhd_type1_init : dummy_vhd_type1 := ( dummy_vhd_type1_sig1 => '0', dummy_vhd_type1_sig2 => '1' ); end package; --- vhdl code: ---- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.dummy_vhd_pkg.all; entity dummy_vhd is port( clk : in std_logic; rst : in std_logic; output_1 : out dummy_vhd_type1 ); end dummy_vhd; architecture rtl of dummy_vhd is signal output_sig1: dummy_vhd_type1; begin output_1 <= output_sig1; proc1 : process(clk,rst) is begin if rst = '1' then output_sig1 <= dummy_vhd_type1_init; elsif rising_edge(clk) then output_sig1.dummy_vhd_type1_sig1 <= output_sig1.dummy_vhd_type1_sig2; output_sig1.dummy_vhd_type1_sig2 <= output_sig1.dummy_vhd_type1_sig1; end if; end process; end rtl; ---- and finally toplevel system verilog: --- import dummy_vhd_pkg::*; module dummy_top_sv ( input logic clk, input logic rst, output logic dummy_sv_1_1 ); dummy_vhd_type1 output_1; assign dummy_sv_1_1 = output_1.dummy_vhd_type1_sig1; dummy_vhd dummy_vhd_inst1 ( .clk(clk), .rst(rst), .output_1(output_1) ); endmodule
06-16-2016 03:53 PM
I would raise a case with Altera MySupport. Their SV support isnt full, and other vendors (cadence in particular) have a terrible time importing records from VHDL in to SV, so this isnt just a Quartus problem.For reference: Modelsim also has a problem with VHDL record that contain arrays that have 0 length, but this is more a System verilog limitation Cadence cannot import any records that contain types other than std_logic or std_logic_vector, and nested records are also not possible.