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getting qsys to find .h and .vh files

Altera_Forum
Honored Contributor II
1,110 Views

okay, so i have a verilog module which is instantiated in a qsys system. 

 

this verilog file has several `includes of header files. 

 

if we write the `includes as relative paths from the location of the main .v file (`include "../includes/foo.vh"), qsys is happy and finds the .h/.vh files while compiling. 

 

however, if we write the includes with no pathname (`include "foo.vh"), qsys can not find the header files. not too surprising since you need to tell most tools what the include directory search path should be. 

 

passing these directories on the ip-generate command line (as --search-path) does not help; this path seems to be telling ip-generate where to look for _hw.tcl files. 

 

so is there some tcl command i can put in the _hw.tcl file which tells qsys where to look for the .vh and .h files? i tried simply "add_file" but this did not work. 

 

thanks.
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2 Replies
Altera_Forum
Honored Contributor II
282 Views

i can see that the command that chokes is: 

 

quartus_map not_a_project --generate_hdl_interface=foo.v --source=foo.v 

 

quartus_map can take an argument, -l, which gives the search path. if i manually construct that command line with the proper -l argument, quartus_map can compile foo.v with its `include "foo.h". 

 

but how in the world do i get ip-generate to call quartus_map like this? do i have to customize the script that ip-generate is running?
Altera_Forum
Honored Contributor II
282 Views

Did you get an answer for this one?  

 

I find that even if you add the Verilog Include files to the "Synthesis Files" list, and set Type="Verilog Include", the invocation of quartus_map to figure out the top level pins is not passed the corresponding -I argument. 

We worked around this by making a sym link from module current directory to the verilog include file, and then checking in the sym links to source code repository (git). The only problem is that this then breaks on Windows :-(
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