glitches in FSM output signals

[Altera_Forum]

Hello..I have a FSM (mealy type). The FSM is coded as three processes. The first process move the state forward on every rising clock edge. The second process only takes care of the state transition based on current state and some input signal. The last process generates output based on current state and some input signal...I did a functional simulation, everything looks fine. but in timing simulations, I have glitches in my output signals... 

 My question is...what are the possible causes of this kind of problem?  I looked closely at my timing simulation...It looks like there's "undefined" state..this is inbetween two defined state..and the output glitches happens here..  any suggestion?

[Altera_Forum]

What kind of glitches? In timing(and in real hardware) everything glitches during a transition. For example, if you have a two registers changing at the same clock edge, the clock will hit them at slightly different times and you will see a "glitch". For example, if going from "00" to "11", you may see 01 or 10 for a few ns. That's life, but it doesn't matter since that glitch goes away before the next clock cycle, and that 01 or 10 is never clocked into the next registers. (You may be seeing a problem glitch where the incorrect value is clocked in, but that's a synchronous design issue.) Not sure if this is what you're talking about, but often something user's mention when going from functional sims to timing sims...

[Altera_Forum]

There is a related current thread at http://www.alteraforum.com/forum/showthread.php?t=4121. That person was concerned about glitches on state machine outputs before realizing that the glitches don't matter if the outputs are used only synchronously by feeding registers. 

 If you are using state machine outputs or any other signal for a clock (usually a bad idea) or asynchronously for something like a reset, then you have to take special measures to prevent the normal glitching that Rysc mentioned.

[Altera_Forum]

If you need your outputs to be glitchless (for instance when interfacing to an asynchronous external part that is sensitive to glitches), a simple solution is to register the outputs. Take into account that the outputs will then be delayed one cycle. This is very simple, common, and recommended in many cases 

 If the extra cycle added makes this solution unworkable, there are manual state machine encoding methods that can prevent glitches by having each output depend on only one state encoding bit (and some inputs, if it is a Mealy machine). This state machine encoding will probably not be the most timing or space efficient.  However, as Brad and Rysc mentioned, you probably don't need to worry about glitches at all, unless you are trying to guarantee specific asynchronous timing.