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hello everyone,
simply put in my design , the DQS strobe goes through LCELLS (to get delays) and drive a register as a clk. currently i have not done constraints to this path because i am not sure how to do that. so when i get the delays through these LCELLS(using timequest) i see that inerconnect delay from the output pad of the DQS strobe to the input of LCELL1 is 1.5ns :eek:. i need to properly constraint this path to remove interconnect delay. can anyone help me with this. thank you, randeel.Link Copied
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