set_output_delay query

[Altera_Forum]

Hi, 

I am currently programming a cyclone III device which amoungst other things has to program a Startix II FPGA on the same board using the FPP configuration mode. The code has been written and simulated but I am having a little trouble getting me head around contraining it properly in Timequest.   Basically I have the an 8bit output bus (WF_DATA) which contains the configuartion data and also the CLK (DCLK), which runs at 66.667MHz.   I have been trying to apply the set_output_delay command but have not been able to successfully apply it.   My .sdc file contains the following commands    create_clock -name {WF_CONFIG_Virtual} -period 15.000 -waveform { 6.000 13.500 } set_output_delay -clock { WF_CONFIG_Virtual } -max $WF_DATA_DCLK_setup ] set_output_delay -clock { WF_CONFIG_Virtual } -min $WF_DATA_DCLK_hold ] where hold is -1ns and setup is 6ns set_max_delay -from * -to 2.000 set_min_delay -from * -to 0.000    To explain what I have done and where my problem lies:   Firstly I created a virtual clock (and I´m not sure if it is specified correctly). this clock comes from a 66.667MHz signal which is phase shifted by 6ns through a PLL. Therefore the clock that is used to assign the data to the WF_DATA bus is done using this shifted clock, therefore the virtual clock has been assinged with a 6ns phase shift. Is my thinking correct here?   As regards the set_output_delay commands, I was reading a previous post on this forum regarding the set_output_delay command and it stated the following : Output_delay(max) = Tsu + DATA delay(max) – CLK delay(min) Output_delay(min) = -Th + DATA delay(min) – CLK delay(max)   I have ignored for the time being the data delay and clk delay as it is unknown and set my constraint using the setup and hold time specified in the Stratix II datasheet (which is actually 0ns hold time and 5 ns setup time, but I added 1ns just to be sure). Given these setup and hold requirements at the destination, am I right in applying the constraint this way?   Finally, the part that is most confusing for me. The clock that is used to clock the data into the stratix II, is passed through a buffer (altclkctrl) as I don´t think I can have it toggling before configuration commences. The buffer is enabled once the first configuration byte is placed on the output bus. I received a warning in timequest telling me that the paths from the input pin of the buffer and the enable pin to the DCLK output pin of the FPGA were not constrained. Therefore I placed the set_max_delay and set_min_delay constaints to constrain it between 0 and 2ns. The problem is that I don´t know how this will affect the the previous set_output_delay constraint. I initially though that by placing the set_output_delay constraint that it would take care of the timings regarding the data bus and the clk.    At the moment I am receiving setup errors in Quartus regarding each bit of the output data bus.    I would be grateful if someone could clarify if my approach to constraining this interface is correct. In particular I would be grateful for any advice on how to deal with the clock which must pass through a buffer between the PLL output and the output pin.   Many thanks for the help.