simulating a desing with DDR3

[eman_delete]

Hello,

I have the Quartus+Qsys design which can be simulated with vcs. This design does have a DDR3 controller in the NIOS block. The design has been never simulated with the DDR3 simulation model.

How do I add the model to the design? Since the DDR3 model is a slave and it's not a part of my FPGA, I don't really care of the type of the DDR3. I just want to see some transactions on the NIOS bus after the init state. What is the simplest way to achieve that? Should I connect the DDR3 model to my DDR3 controller, or should it be done on in the top level? Where can I download a DDR3 simulation model? Are there any examples/documenttion on how to connect and simulate designs with DDR3 models?

Thank you.

[AdzimZM_Intel]

Hello,

I'm Adzim will assist you on this thread.

To generate the DDR3 simulation model, you can get it by generating the DDR3 Example Design from Quartus.

Then you can take the memory model and connect it to your memory controller.

The connection can follow from the Example Design.

This is a reference document for Arria 10 device. Link: https://www.intel.com/content/www/us/en/docs/programmable/683842/21-1-19-2-0/design-example-quick-start-guide-for.html

Regards,

Adzim

[eman_delete]

Hello,

Thank you, for your support. I was able to generate the DDR3 example design and take the memory model from there.

I'm integrating the model in my design now.

Best Regards, Eugene.

[AdzimZM_Intel]

 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.