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Hello!
I was working on a lab code at school and encountered an error in the timequest timing analyze part.
At first, a negative slack error and an unconstrained path error occurred together, but I solved the negative slack error by creating an sdc file with the wizard.
However, I was unable to resolve the unconstrained path error and would like your help.
I still have a limited understanding of quartus, so your help would be greatly appreciated.
Thank you.
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Your .sdc does not include I/O delay constraints (set_input_delay, set_output_delay) so I presume those are what the tool is saying are unconstrained since you don't mention this. You may want to get familiar with timing analysis: https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/timing-analysis-basic-concepts.html
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Hi there, is there any updates on this issue?
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I solved the problem by creating a manual.out.sdc file with input/output delay set to 0 using TimeQuest Timing Analyze.
However, 332043 Overwriting existing clock: error has been added. How should this be resolved?
Thank you.
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You now have two .sdc files? Why? Combine them.
And I/O delays should not be 0 in a .sdc.
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Hi there, please check if there has some conflict constraint on this first, or if the overwriting is a right sdc you can ignore the warning.
As the previous reply, you'd better combine this two sdc file to ensure there is no conflict.
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Hi there, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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