Hi, I was going to make SR clasp for my college assignment.
Why does this error occur? I want to find a solution to this with me.
I attach the picture and the error
Determining the location of the ModelSim executable...
Using: c:/altera/13.1/modelsim_ase/win32aloem/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog latch_s -c latch_s --vector_source=C:/altera/13.1/tukorea_1/Waveform.vwf --testbench_file=C:/altera/13.1/tukorea_1/simulation/qsim/Waveform.vwf.vt
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Mon May 06 20:53:38 2024
Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog latch_s -c latch_s --vector_source=C:/altera/13.1/tukorea_1/Waveform.vwf --testbench_file=C:/altera/13.1/tukorea_1/simulation/qsim/Waveform.vwf.vt
Info (201000): Generated Verilog Test Bench File C:/altera/13.1/tukorea_1/simulation/qsim/Waveform.vwf.vt for simulation
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4604 megabytes
Info: Processing ended: Mon May 06 20:53:39 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory=C:/altera/13.1/tukorea_1/simulation/qsim/ latch_s -c latch_s
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Mon May 06 20:53:40 2024
Info: Command: quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=C:/altera/13.1/tukorea_1/simulation/qsim/ latch_s -c latch_s
Info (204019): Generated file latch_s.vo in folder "C:/altera/13.1/tukorea_1/simulation/qsim//" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4604 megabytes
Info: Processing ended: Mon May 06 20:53:41 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
C:/altera/13.1/tukorea_1/simulation/qsim/latch_s.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/altera/13.1/modelsim_ase/win32aloem//vsim -c -do latch_s.do
Reading C:/altera/13.1/modelsim_ase/tcl/vsim/pref.tcl
# 10.1d
# do latch_s.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module latch_s
#
# Top level modules:
# latch_s
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module latch_s_vlg_sample_tst
# -- Compiling module latch_s_vlg_check_tst
# ** Error: Waveform.vwf.vt(60): near "/": syntax error, unexpected '/', expecting ')'
# ** Error: c:/altera/13.1/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./latch_s.do line 4
Error: can't read "FileWatch(fileName)": no such element in array
Error.
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