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wire assignment in verilog

junyoung2
Novice
999 Views

Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of signal A would be filled with 0, so why would it be filled with 0? Shouldn't it be filled with z or x??

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sstrell
Honored Contributor III
947 Views

No.  Z (high impedance) or X (don't care) are not valid logic levels internal to the hardware of the FPGA.  So anything not defined has to go to 0.  They could be X in a simulation depending on your design if that's what you mean.

Quartus provides warning messages when vector sizes don't match like this.

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junyoung2
Novice
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I found this problem when I was using Questasim from intel. Does Questa define it as a value of zero for unallocated bits? Is there a document to refer to in this regard?

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Kenny_Tan
Moderator
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This is back to Verilog IEEE Standard 1364-2005 (Section 5.1.14) specifies this zero-extension behavior. While QuestaSim adheres to this standard, specific QuestaSim documentation may not explicitly restate this behavior, as it is a fundamental aspect of the Verilog language itself.


If you really want to use it, you will need to write like the below:

assign A = {8'bx, {8{B}}}; // Fills the upper 8 bits with 'x'



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junyoung2
Novice
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The warning message for the bit size does not appear in the Questa Compiler. Is there a way to check if there is a code error for an unallocated bit like the above?

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Kenny_Tan
Moderator
820 Views

I dont think so, you will need to run the simulation waveform to notice this.


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junyoung2
Novice
810 Views

junyoung2_0-1736142448719.png

junyoung2_1-1736142478257.png

Could you look at the two pictures? The signal D defined as 44 bits was divided into 16 bits/16 bits/12 bits and allocated 8 bits each. And as a result of running the simulation, the value of 0 was automatically assigned for the undefined upper bits, and when the value of 1 was given, only the defined 8 bits responded to the value. There was no warning message during the compile process.

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sstrell
Honored Contributor III
777 Views

Can you show the actual code?

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junyoung2
Novice
760 Views

input A;

input B;

input C;

output [43:0] D;

 

assign D[15: 0] = {8{A}};
assign D[31:16] = {8{B}};
assign D[43:32] = {8{C}};

 

I wrote the code like this.

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sstrell
Honored Contributor III
731 Views

So what does your testbench look like?

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Kenny_Tan
Moderator
705 Views

Can you attached your testbench as well, but I think the explanation cannot run far away from my previous comment.


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Kenny_Tan
Moderator
659 Views

Is there any update for this?


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junyoung2
Novice
610 Views

Sorry for the late response. The test bench I made is simply defining those signals and signaling and turning them off one by one over time. I've posted on several forums, but all the answers are 'automatically allocating zero for the remaining bits' in the code I put together. This has been resolved. The only question is whether Modelsim or Questa doesn't warn you about the bit allocation mismatch. Are there any settings that allow Modelsim or Questa to notice warning messages about the bit allocation width?

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Kenny_Tan
Moderator
562 Views

I check the Questasim user guide, I couldn't find an option on this warning message enabling. Since this question is more towards EDA, you may log a case to them to further clarify this. https://www.siemens.com/global/en.html, siemens now officially own questasim.


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Kenny_Tan
Moderator
514 Views

Any further question that you have?


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junyoung2
Novice
506 Views

Then, is there a setting that changes the initial value to x or z, not zero, for the unallocated top 8 bits as in the example above, not a warning message? I wonder how I can check this in the compile stage or in the simulation when the bit width is not correct. Because I automatically assigned 0 for the bit width that is not correct, and if I can't check it in the compile stage or in the simulation, I think this will come to a fatal problem later on.

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Kenny_Tan
Moderator
396 Views

Since this issue pertains to the usage of Questasim commands (TCL), we will need to consult the relevant team for assistance. I have attempted to find an answer in the Questasim user guide located at W:\24.3\linux\questa_fse\docs, but was unsuccessful. We will get back to you, but it may take some time(1 to 2 weeks). Thank you for your patience.



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Kenny_Tan
Moderator
186 Views

Hi,


I just get feedback from Mentor:

For the question regarding warning messages about the bit mismatch, there should be a vopt warning as the example below: 

** Warning: (vopt-2241) Connection width does not match width of port 'data_in'. The port definition is at: dut.sv(3).

if you have vopt.log file generated? You may be able to search vopt-2241 and it should have bit-mismatch warning.


They have also consulted with R&D regarding the question on setting that changes the initial value to x or z, not zero.

According to R&D, currently by default:

Unconnected MSB of type reg will be 0, as this is considered as an assignment.

Unconnected MSB of type wire will be Z, 


Let me know if the above help?


Thanks,



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Kenny_Tan
Moderator
38 Views

Is there any further question on this?


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junyoung2
Novice
33 Views

Thank you for your answer.
I have a question for your answer. For input, don't you write the wire type by default? If so, shouldn't the undefined top bits be allocated as Z? Also, I couldn't find a warning message like vopt-2241 even though the bit was not allocated properly (assign D[15:0] = {8{A}};) and the compilation went well. It seems like Modelsim automatically allocates 0 for the unallocated parts, am I right to understand?

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