Arria 10 SOC h2f_axi_master bus error

[johnt2]

I have a design that is currenly unable to access anything on the h2f_axi_master bus. The LW bus is fine, I can access a couple of onchip memories there. But when I try to access a onchip memory on the h2f_axi_master, I get a buserror. I am building with QII Prime 22.2 Build 94.

I am wondering if there is a enable that was missed. Any tips on how to diagnose this error

would be appreciated. The LW is fine and is connected using the same clock , and reset.

root@achilles-v5-indus:/# devmem 0xc0060000
[ 384.738993] 8<--- cut here ---
[ 384.742048] Unhandled fault: external abort on non-linefetch (0x018) at 0xb6fcc000
[ 384.749583] pgd = fbb268ae
[ 384.752277] [b6fcc000] *pgd=b3c4d831
Bus error
root@achilles-v5-indus:/# devmem 0xc018a000
[ 571.069017] 8<--- cut here ---
[ 571.072071] Unhandled fault: external abort on non-linefetch (0x018) at 0xb6f3b000
[ 571.079607] pgd = a020337c
[ 571.082300] [b6f3b000] *pgd=b3cdc831
Bus error

Thanks,

John

[khtan]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

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[khtan]

Hi John,

Sorry for the delay in replying, may I know whether this issue is still persisting on your end and still requires support ?

Thanks

Regards

Kian

[khtan]

Hi,

As we do not receive any response from you on the previous reply. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks

Regards

Kian