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QSPI read write

Oaksys
Beginner
360 Views

Hello. I am writing and reading to a Infineon S25FL512S memory with alt_qspi_write and alt_qspi_read.

I write a small block of data and gets this result

Write:

0x87654321
0x87654321

Read

0x72583614
0x7F583614

Write:

0x87654321
0x87654321
0x87654321

Read

0x72583614
0x72583614
0x7F583614

Data data is scrambled and the last word always get a 0xF at the highlighted position. I have another hardware with a Micron N25Q512 memory that does not behave like this. Any ideas?

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1 Solution
aikeu
Employee
207 Views

Hi Oaksys,


Not sure will this help which relates to the dummy cycles, It mentioned that "Third-party quad SPI flash devices may have fixed or configurable dummy clock cycle":

https://www.intel.com/content/www/us/en/docs/programmable/683271/current/understanding-dummy-clock-cycles-for.html


Anyway I will close and transition the thread to community support since the issue has been resolved.


Thanks.

Regards,

Aik Eu


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3 Replies
aikeu
Employee
320 Views

Hi Oaksys,


I do not understand your write and read operation sequences from your provided examples.

Would like to know if the data error only happened on a specific address only or there is an inconsistency in the write/read process?

For example, everytime you write something, does the written data valid after read?

Or there is data error on specific location whereby the data doesnot change after write which is the 0xF that you noticed?

Make sure to perform erased first before a write and see if any difference.


Thanks.

Regards,

Aik Eu


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Oaksys
Beginner
307 Views

Sorry for the vague error description. I found the issue in the hwlib file alt_qspi.c. After changing the read_dummy_cycles for the S25FL512S memory from 7 to 6 everything is working fine. If anyone has a good explanation why this hack works for my setup I will be thankful.

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aikeu
Employee
208 Views

Hi Oaksys,


Not sure will this help which relates to the dummy cycles, It mentioned that "Third-party quad SPI flash devices may have fixed or configurable dummy clock cycle":

https://www.intel.com/content/www/us/en/docs/programmable/683271/current/understanding-dummy-clock-cycles-for.html


Anyway I will close and transition the thread to community support since the issue has been resolved.


Thanks.

Regards,

Aik Eu


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