Unable to run Generic Serial Flash Interface IP at 100 MHz

[Jpasquiet]

Hi, 

I am working on a Cyclone V, writing an epcq128A using Generic Serial Flash Interface Intel IP. 

After integrating the IP and connected it to the HPS in the platform designer, I am now able to do so using C bare metal and pointers dereferencing. 

My point is that everything works perfectly at a low frequency, when the IP is connected to a 50 MHz pll and a 32 times clock divider set on the IP. However, when I am trying to write to the EPCQ with a 100 MHz pll and a 4 times clock divider or lower, my processor crashes during my memcpy call. 

NB : This behaviour only concerns writing, I can read at those frequencies without problem.

I saw on the reference manual that the clock IP can be pushed up to 100 MHz. So I am way below the limits. 

My control registers are set as below :

• Addressing mode : 4 bytes addressing 
• Chip Select : 0x0 to select the first device since I only have one. 
• SPI Baud rate divisor : from 32 to 2, but below  4 times dividor, the µC crashes
• CS Assert : set to 5, as mentioned in the RM.
• Write and Read instruction are set accordingly to the epcq's datasheet 

Regards

Versions : 

• Quartus Prime 2018
• Generic Serial Flash Interface Intel IP 18.0

[Fakhrul]

Hi Jpasquiet,

I'm sorry I missed your post. There's a KDB though it may not be directly related to your issue, can you check this- Why does the Generic Serial Flash Interface Intel® FPGA IP fail to deassert nCS in write enable operation? and try with Quartus Prime software version 20.3

Regards,

Fakhrul

[Fakhrul]

Hi Jpasquiet,

I wish to follow up with you on this case. Do you still have further inquiries on this issue? Please feel free to let me know if there is any concern so that we could further assist you.

Otherwise, this thread will be idling and marked as inactive, thus it will be transitioned to community support because there is no update received from you in a while.

Regards,

Fakhrul

[Jpasquiet]

Hi @Fakhrul , 

Thank you for your time and your answer.

I've switched to another task for the moment, thus I havn't been able to try adding more of interval cycles between instructions from CSR port as mentionned on the post, however I am keeping this information in mind and I'll not miss to mark this topic as solved if it works.

Best regards,

Jpasquiet

[Fakhrul]

Hi Jpasquiet,

Thanks for the feedback.  Since it is not recommended to idle for too long. Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience caused.

Hence, This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Regards,

Fakhrul