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10 bit expectation... where should the 10 bits be?

RobinsonUK
New Contributor I
1,971 Views

For input data in 10 bit format to an AV1 encoder I use MFX_FOURCC_P010.   Now the comment in the header says, "P010 color format. This is 10 bit per sample format with similar to NV12 layout. This format should be mapped to DXGI_FORMAT_P010".  It says nothing about whether the input data should be in the high or the low 10 bits and whether or not the remaining 6 bits should be zeroed out.  I have the same issue with decoder output.   As the comment says "should be mapped to DXGI_FORMAT_P010", I assume the data should be in the high 10 bits as that is what DXGI_FORMAT_P010 asserts.

 

I have noticed that NVIDIA'S NVENC expects data in the MSB for its NV_ENC_BUFFER_FORMAT_YUV420_10BIT, with the following comment: "10 bit Semi-Planar YUV [Y plane followed by interleaved UV plane]. Each pixel of size 2 bytes. Most Significant 10 bits contain pixel data."  Again it doesn't state whether the data should be zeroed out but let's assume we do this for the sake of argument (seems sensible).

 

So, my pipeline contains data in the LSB, which implies for NVIDIA (and probably Intel) AV1 encoding I have to shift it this way << 6 .  After decoding at the other end I have to shift it back again >> 6.  This is fine and indeed the software seems to work correctly when I do it.

 

Using the DAV1D decoder and passing it a bitstream encoded with MSB format, it appears to already be in the LSB so no shift is needed.  This has confused me somewhat as it's accepting data in the MSB and producing output already shifted.  Again (3rd time) behaviour is undocumented.  Finally, I think FFMPEG (libav1) also writes to the MSB.  At least to get it into my LSB pipeline it seems I need to shift it down >> 6.  That is again undocumented. (yes there's a pattern here: never document expectations and behaviour, make the developer figure it out through trial and error).

 

So my question is does Intel's AV1 10 bit encode/decode functionality document what is needed?  If so, where?  I've scanned the AV1 standard and it doesn't appear to be mentioned at all.

 

Thank you.

 

6 Replies
JaideepK_Intel
Employee
1,908 Views

Hi,


Thank you for posting in Intel Communities.


To understand your issue better, could you please share the below information?

  1. Which tool you are using MSDK/OneVPL?
  2. Are you facing this issue on specific hardware(CPU) or is it on all the platforms/hardware?
  3. please share the OS and processor details (if this issue is related to specific hardware)


Thanks,

Jaideep


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RobinsonUK
New Contributor I
1,888 Views

Thanks Jaideep,

 

This is a general question that applies to Media SDK and OneVPL.  We use both to support older hardware.   I think I know the answer but don't see it documented anywhere.  I'm on x86, Windows.  I have an Arc setup with an AMD CPU and a Coffee Lake setup (8400) using CPU.  The latter does not support AV1 but does support HEVC 10 bit (but no b frames).  I think input data has to be in the high ten bits for P010LE (MFX_FOURCC_P010) and the output from any 10 bit decode is also in the high 10 bits.

 

It's not an issue as such as I can figure it out duing testing (garbage in, garbage out).  I just want to know what the officially correct answer is, i.e. to where do I point in documentation.

 

A comment in the source file says, "This format should be mapped to DXGI_FORMAT_P010".  Looking up DXGI_FORMAT_P010 I see that . it states, "The runtime does not enforce whether the lowest 6 bits are 0 (given that this video resource format is a 10-bit format that uses 16 bits)".  This is just implying the upper ten bits are where the information is, without explicitly saying so.  It's not documented anywhere in the SDK but I assume it's the same for Media SDK, One VPL, encode (encode expects it in the msb) and decode (delivers it to the msb).

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Pamela_H_Intel
Moderator
1,733 Views

Thank you for the detailed info. I am checking with the GPU Runtime team.


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Pamela_H_Intel
Moderator
1,659 Views

Robinson,


One of our devs verified in the code . . .


Your assessment is correct, for P010, whether or not the lower 6 bits are zeros, the data is in the upper 10 bits.


Pamela


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Pamela_H_Intel
Moderator
1,648 Views

FYI - I've created a Jira for the docs to be updated to include this info.

You are justified in your frustration that you need to do trial and error to figure out which bits to put your data in. We appreciate you pointing this out so we can improve our docs.

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RobinsonUK
New Contributor I
1,567 Views

This is great.  Thank you very much Pamela.   You can close this ticket.

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