Nios® II Embedded Design Suite (EDS)
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12497 Discussions

Boot HPS from FPGA doesn't work

Honored Contributor II



Has anyone succeeded in booting preloader from FPGA On-Chip RAM (OCRAM)? For now I can mannually load preloader through the JTAG in DS-5 debugger. It executes well and then a simple application is loaded to SDRAM and also executes. But the prime interest is to boot preloader from FPGA On-Chip RAM after FPGA configuring. I've used as an example and user guide. In DS-5 I've checked from address 0xC0000000 (FPGA OCRAM address from HPS point of view) and there is preloader data. It's expected these commands is moved to 0xFFFF0000 region by the BootROM after reset, if BSEL = 0x1 and signal Boot_from_FPGA_ready = 1, and executes. But if I set jumpers to make BSEL = 0x1 and reconfigure FPGA, nothing loads. Furthermore, if I connect DS-5 debugger, it says CPU is running. While I try to stop it and view internal state the error occures: 

ERROR(TAD9-NAL30):# in C:\eclipse_work\Altera-SoCFPGA-HardwareLib-FPGA-CV-ARMCC\test.ds:1 while executing: stop ! Unable to stop device Cortex-A9_0 ! Cannot stop target. ERROR(CMD656): The script C:\eclipse_work\Altera-SoCFPGA-HardwareLib-FPGA-CV-ARMCC\test.ds failed to complete due to an error during execution of the script 


Next, I've tried to reset CPU under the DS-5 debugger, by writing 

reset system 


The log is 

Target has been reset Execution stopped at: S:0x00000000 S:0x00000000 LDR pc, ; = 0xA8 


But if I try to examine memory, an error occures: 

Target Message: Could not determine target state 


In the article above they say after configuring FPGA part preloader info could be viewed in UART console. But in this case nothing is printed in console, of course. 


So can anuone say how to boot HPS part from FPGA? Where is a trick? Any useful links or ideas will be beneficial. 


My board is Arrow SoCkit. Quartus II 14.1 & ARM DS-5 5.20 are used. 


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2 Replies
Honored Contributor II

I have done it with the documentation from [1] and it worked for the Arrow-SoC-Kit, the EBV-SoCrates, the CVSoC Development Board from Altera and our custom-Board. 




Honored Contributor II

Hi, Sören, this is really good news to me! I've studied 2 documents carefully: [1] ( and [2] ( And I am confused by the different preloader settings they give. Can you share your preloader settings to boot from FPGA OCRAM, please? And also for Arrow-SoC-Kit board, how have you routed reset signals to HPS? I've done this way: 

.hps_cold_rst_reset_n ( HPS_RESET_n ), .hps_debug_rst_reset_n ( HPS_WARM_RST_n ), .hps_warm_rst_reset_n ( HPS_WARM_RST_n ), 

And signals HPS_RESET_n & HPS_WARM_RST_n I've simply added to the port list, Quartus routed it by itself. I think some mistakes are possible..  

As I've understood we load .sof file, pass a cold reset to HPS and then some response in my UART terminal is expected, right?