How can I get data from FPGA frabic via FPGA-to-HPS?

[Altera_Forum]

Hello, 

 I implement the a soft-IP AXI master in FPGA and transmit the data to HPS side via FPGA2HPS bridge, I set ACP-port as "dynamic" mode. BUT how can I read the data via DS-5 program register?  I know maybe need set the sideband signals and use the mirrored Main-Memory in the ACP window, but not to the location directly(e.g. I want to access 0x0030000 I need to access 0x80030000). Does it correctly?

[Altera_Forum]

Hi Alex, 

Please refer to the Getting Started with Peripheral Register Visibility section of the SoC EDS User's Guide (http://www.altera.com/literature/ug/ug_soc_eds.pdf). I think that should answer your question. Regards, Sue

[Altera_Forum]

--- Quote Start ---  Hi Alex, Please refer to the Getting Started with Peripheral Register Visibility section of the SoC EDS User's Guide (http://www.altera.com/literature/ug/ug_soc_eds.pdf). I think that should answer your question. Regards, Sue  --- Quote End ---   Hi Scozart, Thank you for your reply!  But my question is that I cannot get data from fpga2hps bridge via Arm-Linux Application. In my design, the following steps I used in my project: 1. The FPGA master have been implemented in FPGA2HPS bridge, I used the signals (user sideband signal, write address signal, write address valid signal, write data signal, write data valid signal ) 2. In ARM side, I use the ACP ID Mapper Register. The dynrd and dynwr registers has been set the 5-bits user(according to user sideband signal) and 2-bits Page(I remap the 3rd 1GB memory). 3. I maped the address in Linux application , access to e.g. 0x80004000 (3rd page) address, but the data have not changed .   Did I miss some steps? Or misunderstand something?

[Altera_Forum]

Hi scozart, 

Thank you for your reply! But my question is that I cannot get data from fpga2hps bridge via Arm-Linux Application. In my design, the following steps I used in my project: 1. The FPGA master have been implemented in FPGA2HPS bridge, I used the signals (user sideband signal, write address signal, write address valid signal, write data signal, write data valid signal ) 2. In ARM side, I use the ACP ID Mapper Register. The dynrd and dynwr registers has been set the 5-bits user(according to user sideband signal) and 2-bits Page(I remap the 3rd 1GB memory). 3. I maped the address in Linux application , access to e.g. 0x80004000 (3rd page) address, but the data have not changed .   Did I miss some steps? Or misunderstand something?

[Altera_Forum]

Hi Alex, 

Sorry for the delay in responding. It looks like you may be having a problem with cache coherency. Please check the follow items in your system: 

• The SMP bit in the ACTLR register in the ARM core must be set before enabling the MMU. This should be done by the OS, but it is good to check. 
• The SCU must be on. 
• The memory space should be marked as shared and the secure bit must be set the same for the FPGA master and the HPS. 
• The cache properties must be the same for the FPGA master and the HPS and you should use write allocate for the cache. 
• The ARUSER and AWUSER bits in the ACP ID Mapper registers should be set to 5'b11111. 

 Please let me know if these suggestions solve your problem. If not, we'll look further. Regards, Sue

[Altera_Forum]

--- Quote Start ---  Hi Alex, Sorry for the delay in responding. It looks like you may be having a problem with cache coherency. Please check the follow items in your system: 

• The SMP bit in the ACTLR register in the ARM core must be set before enabling the MMU. This should be done by the OS, but it is good to check. 
• The SCU must be on. 
• The memory space should be marked as shared and the secure bit must be set the same for the FPGA master and the HPS. 
• The cache properties must be the same for the FPGA master and the HPS and you should use write allocate for the cache. 
• The ARUSER and AWUSER bits in the ACP ID Mapper registers should be set to 5'b11111. 

 Please let me know if these suggestions solve your problem. If not, we'll look further. Regards, Sue  --- Quote End ---    Hi Scozart,  I also have the same question for the thread. I am using the SoCKit board with Linux. I write an AXI master in System Verilog. This master is integrated into Qsys and connected to the FPGA-to-HPS bridge. In my test, this AXI master can access FPGA-RAM. However, It can't access HPS-RAM. In this situation, the written address of this AXI master is the virtual address obtained by malloc() in Linux. The ARUSER and AWUSER pins of this AXI master are set to 5'b11111. The AWCACHE and ARCACHE pins of this AXI master are set to 4'b1111. I write a program in Linux to check whether the data at the virtual address is the same as the written data of this AXI master. The result is that the data at the virtual address in Linux is not changed.  Thank for your attention. --AJMachine