Where are hwlibs for Cyclone V SoC HPS EMAC?

[corestar]

I need to write a driver for the HPS EMAC. The rev 18.0 hwlibs do not seem to have any functions to control the EMAC.

I'm used to Xilinx Zynq which has a large API of functions in the BSP to do things such as XEmacPs_CfgInitialize to initialize and EMAC, XEmacPs_SetMacAddress, and XEmacPs_SetHandler to set interrupt handlers etc. Is there nothing similar in Altera????

[Abe]

The HWLIBS for Cyclone V SoC are present only in the Standard Version of Quartus Prime and EDS only. The Pro version will support only Cyclone 10, Arria 10 and Stratix10 SoCs.

[corestar]

@Abe​ , I'm using the Quartus Standard since Pro does not support Cyclone V at all. But there don't appear to be any hwlibs for the EMAC.

[corestar]

To be more specific, I've attached a screenshot the HWLIBS docs. A large number of functions for things such as the UART, I2C etc, but nothing for the EMAC.

[Abe]

Looks like only the Register space for the EMAC is defined in the HWLIBs. I do not see any API documentation. You can find this information under Address Space -> Component: EMAC Module - ALT_EMAC.

Intel (Altera) does mention the following:

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

Looks like we have to write our own drivers for the EMAC using the register space provided and the alt_write_word() and alt_read_word() functions.

If you look into the following location you will find the emac header file:

/intelFPGA/18.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av/socal