Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.

AXI3 Lightweight Bridge

Altera_Forum
Honored Contributor II
1,249 Views

Hi All, 

 

I have a question about the AXI3 Lightweight bridge coming from HPS toward FPGA portion... 

 

How can I define a clock frequency for the AXI3 Lightweight bridge? I cannot find the appropriate field in the Qsys HPS section...  

 

Thank you!
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
265 Views

The HPS2FPGA AXI Bridge has many periph_id registers. What are they used for? It's not so understood...

0 Kudos
Altera_Forum
Honored Contributor II
265 Views

You have to select the Bridge in the HPS configuration (I think first Tab in QSYS) and afterwards connect a clock within the Top-Level Qsys-Design to it.

0 Kudos
Reply