Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12627 Discussions

Address missmatch in triple_speed_ethernet tutorial when setting Block Diagram as Top

Honored Contributor II



i have a Verilog file from the tutorial: "Using Triple Speed Ethernet on DE2-115 Boards" 


I am trying to build the same verilog file in a Block diagramm and set it as a Top Entity.  


In the verilog file, i have 3 Instances. I took the Instances and added them seperatly to the Block Diagramm. 


My project ist working fine with the Verilog file as Top entity.  


When i set the Block diagramm as Top Entity, i get some problems in Eclipse: 


Verifying 00080000 ( 0%) 

Verify failed between address 0x80000 and 0x86183 

Leaving target processor paused 


I compared the designs in RTL viewer. Both designs in RTL Viewer look alike ! 


Anyone have a clue whats going wrong ? 


I need to seperate the 3 Inst. in the Block Diagramm and i cant use the option "create Symvol Files for current file" !!
0 Kudos
0 Replies