Nios® V/II Embedded Design Suite (EDS)
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Audio keeps on looping

Honored Contributor II



I`m a beginner at working with the altera FPGA de2 board and I need some advice. 

Currently i´m trying to read an audio sample and change it into an echo in C. 

I got the line in and line out working, but the problem now is that i´m always getting an output(it´s looping) before running the C code. 

What i want is that I only get an audioinput when I ask it and send it to the line out in the NIOS II C. 

I don't know if this is something i need to do in quartus VHDL or in C. 

Can somebody help me? 




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