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Check FPGA / bridges before accessing them

Altera_Forum
Honored Contributor II
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I want to access the switches on the tersIC DE0-Naoo-SoC board from Linux. I load the appropriate FPGA and access the LW bridge (with a c program). Everything works fine. 

 

But if, due to eg. misconfiguration, the FPGA is not loaded with the appropriate file the Linux programm will hang forever when accesing the bridge. Thus stopping the complete system! 

 

Is there a way to check from Linux if the address I want to access will work? 

 

Joachim
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Altera_Forum
Honored Contributor II
452 Views

If I am not mistaken, you can check the status of the bridge via: 

cat /sys/class/fpga-bridge/fpga2hps/enable 

cat /sys/class/fpga-bridge/hps2fpga/enable 

cat /sys/class/fpga-bridge/lwhps2fpga/enable 

 

https://rocketboards.org/foswiki/view/documentation/gsrd131programmingfpga
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Altera_Forum
Honored Contributor II
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Hi sunshine, 

 

the bridges are enabled: 

 

root@jwde0soc:~# cat /sys/class/fpga-bridge/lwhps2fpga/enable 

root@jwde0soc:~# cat /sys/class/fpga-bridge/hps2fpga/enable 

root@jwde0soc:~# cat /sys/class/fpga-bridge/fpga2hps/enable 

 

Still the program hangs when reading from an lwhps2fpga-Address (mapped with /dev/mem). 

 

Joachim
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Altera_Forum
Honored Contributor II
452 Views

 

--- Quote Start ---  

Hi sunshine, 

 

the bridges are enabled: 

 

root@jwde0soc:~# cat /sys/class/fpga-bridge/lwhps2fpga/enable 

root@jwde0soc:~# cat /sys/class/fpga-bridge/hps2fpga/enable 

root@jwde0soc:~# cat /sys/class/fpga-bridge/fpga2hps/enable 

 

Still the program hangs when reading from an lwhps2fpga-Address (mapped with /dev/mem). 

 

Joachim 

--- Quote End ---  

 

 

Looks like checking the bridge status may not be a viable option... since the hang happen if the FPGA is misconfigured, perhaps another way is to use the HPS FPGA manager to ensure that the configuration is executed successfully?
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Altera_Forum
Honored Contributor II
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You can check the state of the FPGA configuration with: 

cat /sys/class/fpga/fpga0/status  

 

A well configured FPGA should return: "user mode".
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Altera_Forum
Honored Contributor II
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Nope. The FPGA is configured sucessfully. But with the wrong rbf. 

 

The main problem is if some setup is wrong the FPGA does not have a register at the address I access.  

I could figure out from my software if I get a valid result. But the whole systems hangs after an access.  

So I am looking for a way to check prior to accessing the address. 

 

My customers want to build a drives control system with this and they don't like that some Linux process can hang up the whole system by just accessing a wrong address.
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Altera_Forum
Honored Contributor II
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This sounds like a design bug. Do you have any idea, why the the system hangs up? The only reasons i had so far are: 

  • unconfigured FPGA 

  • missing bridge in design 

  • FPGA Design in reset, or missing clock 

  • wrong handled waitrequest in design 

  • timing issue 

 

If you have several designs you could identify them with the GPI Pins from the HPS. There is no risk of hanging up.
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