Constraints file for D10-Lite Computer_System from Intel FPGA University Program

[kodachi77]

I've downloaded version 21.1 of Intel FPGA University Program and started to experiment with NIOS II computer system for DE10-Lite. When I try to perform full compilation the design fails timing analysis. Setup time slack for system clock is -931ns and for ADC clock -12ns.

SDC file looks like a vanilla file from any Altera design.

create_clock -period "50.0 MHz" [get_ports CLOCK_50]
create_clock -period "50.0 MHz" [get_ports CLOCK2_50]
create_clock -period "10.0 MHz" [get_ports CLOCK_ADC_10]
create_clock -period "100.0 MHz" [get_ports DRAM_CLK]
derive_pll_clocks
derive_clock_uncertainty

Would it possible to share detailed file that allows to achieve timing closure for this design? This will be really helpful since it is hard to come by fully specified constraint files for DE boards.

Main areas of interest: IO input/output delays, multicycle and false paths.

Thank you!

[ShengN_Intel]

Hi,

Can share the link where you download the design?

Thanks,

Best Regards,

Sheng

[kodachi77]

The design is a part of the Monitor Program install that can be found here: https://fpgacademy.org/tools.html

After installation it can be found in the following directory:

.../intelFPGA_lite/21.1/University_Program/Computer_Systems/DE10-Lite/DE10-Lite_Computer

[ShengN_Intel · Accepted solution]

Hi,

DE10-Lite_Computer is a general design example for the manual DE10-Lite_Computer_NiosII.pdf.

You may refer to DE10-Standard_Computer design example for more completed sdc constraints file.

Thanks,

Best Regards,

Sheng

[kodachi77]

Thank you, this helps!