Critical Warning (332012): Synopsys Design Constraints File file not found: 'niosii_ethernet_standard_5CGTFD9E.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
I was trying to synthesize NIOS II simple socket server reference design (https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/nios-ii-simple-socket-server-ethernet-example-for-cvgt/) . But I was getting this critical warning stating that the sdc file is Missing. Can anyone help what constraints have to be included to check the timing analysis of this project?
I have seen and downloaded the design file. Checked the file turn out there is no niosii_ethernet_standard_5CGTFD9E.sdc in the cvgt_simple_socket_server_project directory on my side. Can you verify it from your side and let me know.
Hello... This *might* be an answer. But I think there is a bug in Quartus Prime Lite (version 19.1) running on Ubuntu 16.04.
I have found that the timing analyzer can't find lower case .sdc filename extensions. For example it can't find "MyProject.sdc" but it does find "MyProject.SDC".
Note that the "main" quartus program is also sensitive to the case, but as long as you tell it the right name, it finds it. So the bug is specific to the timing analyzer. A work-around is to start new projects with the Synopsis Design Constraint file(s) always having the extension .SDC - uppercase.
Perhaps this is a bug from porting code from MS-DOS and early versions of Windows which treated all file names as uppercase?
PS: I'm new to this biz. How does one officially tell Intel about a suspected bug?
I guess I don't have the sdc file at all in the project specified. So I cannot decide the validity of your query. But I will try to look into it and see if I face the similar issue. You can message this person https://forums.intel.com/s/profile/0050P000008xvavQAA who is from Intel. Thanks!