Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
12517 Discussions

Cyclone III - Nios II - Starter board

praveenkumar
Beginner
369 Views

On programming through jtag (usb blaster)

verify failed between onchip memory locations some xxxxx and xxxx.

 likethat it showing an error anyone help me about this

0 Kudos
2 Replies
YuanLi_S_Intel
Employee
349 Views

Hi,


Can you show me the exact error message that you got?


Also, how do you do programming? Are you programming the FPGA using Quartus Programmer or via NIOS II?


Regards,

Bruce


praveenkumar
Beginner
336 Views

i am programming   with both   .sof file from quartus programmer and .elf file from nios ii.

while programming from quartus programmer its working fine .but on loading with nios ii .its comming error verify failed betweeen memory locations   0x40000and 0x43270 like that i dont understand the cause of this error.

jtag is detecting .

and also i have another doubt .

while assigning the pin assignments in cyclone iii

part number EP3c80ufbga484i7

error shows while compiling like can't  fit the design in fitter and placing.

 

can't place multiple pins assigned to pin location D1,k1,e2.

i checked all the other pins i didnt place these any where in pin planner .

its showing pin d1 assigned to ALTERA_ASDO_DATA

pin e2  to ALTERA_FLASH_nCE_nCSO.

like that.

but we didnt route these pins to those assigned pins.

 i want to know if these pins are reserved or something else

please find a solution for this also

Reply