Cyclone V FPGA-to-HPS Bridges design example bug?

Altera_Forum · ‎06-22-2018

I found what appears to be a bug in the example_design.c file, but didn't see a means to report it directly. So, I'm posting it here.

example_design.c:233

    for(int i=0; i<test_set->hardware_instances; i++)
    {
        test_set->bg_counters = 0;
    }

should be

    for(int i=0; i<test_set->hardware_instances; i++)
    {
        test_set->bg_counters = 0;
    }

Altera_Forum · ‎06-25-2018

Hi,

Thanks for notifying the bug, let us check/workaround it.

We will get back to you on this as soon as possible.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)