Hi all,
I'm working on a design right now that needs to use the PCIe Hard IP on both the HPS and the NIOS II at the same time (for compatibility with some old designs). As a starting point I am using the Rocketboards PCIe Root Port with MSI design to which I have added a NIOS II core with it's own On-Chip RAM and JTAG UART. I am using the Altera Cyclone V SOC board with a PCIe ethernet adapter attached as a test.
The HPS will always be running, so I'd like to have it configure and enumerate the PCI Express devices through Linux. The NIOS will also have to be able to read the device and vendor IDs though because a few different PCIe endpoints will be attached. My initial thinking is to use the Cra Avalon Slave and connect that to the NIOS. However, after reading through the PCIe documentation on Altera's website, I can't seem to find (or understand) an explanation of the how the Cra interface should actually be used to send and receive data.
Any help or suggestions on relevant documentation would be greatly appreciated.
Thanks,
Faraz
