DE0 with uClinux

[Altera_Forum]

Hi, 

  cant configure device.expected jtag ip code 0x020f3000 for device, but found jtag id code is 0x020f2000.How resolve this problem.   Kindly any help?

[Altera_Forum]

It looks like you didn't specify the correct FPGA device in your Quartus project.

[Altera_Forum]

Thanks for reply, i seleted correct device, it working now.And i wants to download image into DE0's SDRAM, but its not downloading, it showed error like 

 pausing target processor:not responding. resetting and trying again:failled. leaving target processor paused.  Kindly any help?   Thanks, Alex

[Altera_Forum]

Usually when the CPU isn't running it means it isn't receiving a clock or its reset signal is wrong (wrong polarity for example).

[Altera_Forum]

helo sir, 

  Please Can u tel me what r the things , i have to add DE0 SOPC builder?  i added the following things , anything else i have to add or how to find out the following things correctly added or not to SOPC builder??  1.SDRAM, 2.altpll_sys 3.cpu. 4.jtag_uart 5.timer_0 6.PIO_LED.   Thanks, Alex.

[Altera_Forum]

This seems to be enough. I would just add a system ID component to help you later if you have an inconsistency between your hardware and software configurations, but anyway the lack of system ID isn't the reason of your problem here. 

Try and use signaltap to monitor the reset signal (remember, the reset input on a SOPC builder system is active low, not high) and the locked signal from the altpll_sys.

[Altera_Forum]

I don't understand your list, those don't all look like signal names. The SDRAM signal names should correspond to those from the controller, and the pll clock input should be connected to an on board oscillator.

[Altera_Forum]

Helo sir, 

 What i did means  1.Created a new project nd i copy & paste the DE0_Nan0's quartus file.---> save. 2.SOPC builder 3.Pin assignments 4.Downloaded the .sof file-------->working. 5.I tried to download zImage into DE0's SDRAM,  Is this procedure is correct? if is correct means , where is the mistake?why image is not downloading into SDRAM?Why above error is coming?  Thanks in advance, alex.

[Altera_Forum]

It should work. You may have made a mistake in the pin assignments,especially the clock signal. Use signaltap to see if you have valid clock and reset signals in your system.

[Altera_Forum]

Thanks sir, i will check nd l inform whether it is working or not.And today i created some projects, but its not downloading through command line.It showed error llike 

 error(213010) programming file /home/alex/.qpf is not a legal programing file-----specify a legal programing file.  What is this, iam using quartus 11.1version.   And how uninstall quartus on linux?is it simple?      alex.

[Altera_Forum]

You probably aren't giving the right instructions on the command line, as the error message suggests "/home/alex/.qpf" doesn't look like a valid file name.

[Altera_Forum]

Thanks you sir, there is a pin assignments problem,now i rectified, but it showed another error 

 Using cable USB-Blaster [7-1] , device, instance 0x00 pausing target processor ok Initializing CPU cache (if present) ok Downloaded 1350kb in 267s(505kb/s) verified 000000(0%) verify failed between add 0xD00000 & 0xD02AA5 leaving target processor paused.   Where is the mistake?  Thanks , alex.

[Altera_Forum]

This is probably something wrong with the SDRAM interface. Either bad pin assignments or bad timing. 

If you FPGA is big enough you could design a system with some on-chip RAM and then run a memory test application from there to test the SDRAM. For that you will need to create a new BSP that uses the on-chip RAM for all sections (text, bss, data), compile with "optimize for space" and the small C library, and select the memory test template when you create your application.