DMA with NIOSII

[fpgaSoft]

Hi, I am using a Cyclone 10 FPGA with NIOS for a project and I am running into a few problems with the DMA IP block.

The DMA block in question is the Modular Scatter-gather DMA IP, in memory-mapped to stream mode.

I have the stream output going into signal tap to look at the data. Some of the time the data looks ok. i.e the data is available as soon as the source_valid goes high, the VALID is high for the 4x32 bit words I am sending.

However every now and then VALID is only high for one of the blocks of data, some are before it. I could be doing something wrong but according to the IP, VALID should be rasied when there is valid data &  not after.

Is there something I am doing wrong? Or is this actually expected behaviour? If so how do I account for that, given I only the limited lines i have out of the block?

Best regards

[KellyJialin_Goh]

Hi,

Greetings and welcome to Intel's forum.

You may refer to this Youtube video on how to enable MSGDMA with NIOS II: https://www.youtube.com/watch?v=iaRkjkpMBH8 and the embedded IP user guide on MSGDMA for more information: https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/modular-scatter-gather-dma-core.html

Hope to hear on your feedback. Thank you.

Regards,

Kelly Jialin, GOH

[KellyJialin_Goh]

Hi,

Any updates from your end whether the information provided was useful?

Thank you.

Regards,

Kelly

[KellyJialin_Goh]

Hi,

Any updates from your end whether the information provided was useful?

Thank you.

Regards,

Kelly

[fpgaSoft]

Hi Kelly,

sadly the information didnt help as to why the data is being sent out before the VALID line is asserted. I have ended up going back to using the memory-mapped to memory-mapped version of the DMA. However the streaming version does look more appropriate for my design so it would be good to know why it doesnt appear to be working properly

Best regards

[KellyJialin_Goh]

Hi,

Is there any further support needed from my end? Hope to hear on your feedback.

Thanks.

Regards,

Kelly

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