Hi everybody,I hope you're well. I've been working several days with meta-layer, because I'm working in a custom Altera SoCFPGA board trying to put linux, and I have two questions. Well my problem by now is when I try to boot with the compiled image from Yocto using bitbake, it stops in DRAM initialization step like in the photo. http://www.alteraforum.com/forum/attachment.php?attachmentid=12672&stc=1 maybe i'm not compiling the right u-boot? should i configure any hardware? I mean... in the U-Boot header I read "U-Boot 2016.05" but the actual branch in https://github.com/altera-opensource/u-boot-socfpga is based in 2013.01.01 like the preloader. And it looks like a misconfiguration of hardware, so for example I don't have any I2C peripheral and it is trying to configure it until times out. But in the recipe of altera layer in Yocto. meta-altera/recipes-bsp/u-boot/u-boot-socfpga_2016.05.bb it looks like it's based in a newer version.
Paths in bblayers.conf are set, and in local.conf file I've changed the MACHINE and added the followings lines: MACHINE = "cyclone5" PREFERRED_PROVIDER_virtual/kernel = "linux-altera" PREFERRED_VERSION_linux-altera = "4.6%" GCCVERSION = "linaro-5.2" SDKGCCVERSION = "linaro-5.2" DEFAULTTUNE = "cortexa9hf-neon" BB_NUMBER_THREADS ?= "8" PARALLEL_MAKE ?= "-j 8" thank you in advance =)
If I am not mistaken, you need to generate the Preloader from the EDS tool (bsp-editor) as this will let the software knows which peripheral is enabled (via the handware handoff files). Then, you can create your own uboot (make sure to append the header so that the preloader will load it) instead of the one that the EDS tool generates.
--- Quote Start --- If I am not mistaken, you need to generate the Preloader from the EDS tool (bsp-editor) as this will let the software knows which peripheral is enabled (via the handware handoff files). Then, you can create your own uboot (make sure to append the header so that the preloader will load it) instead of the one that the EDS tool generates. --- Quote End --- In first place thank you for your response. :) Yap! Preloader was generated with bsp-editor and then I executed "make" command in a Embedded Shell in spl-bsp folder, and preloader-mkpimage.bin was generated. Until here everything fine! =) Next step in the boot flow is the bootloader, so following this tutorial from Rocketboards I tried to generate an image: https://rocketboards.org/foswiki/view/documentation/yoctodorabuildwithmetaaltera (https://rocketboards.org/foswiki/view/documentation/yoctodorabuildwithmetaaltera) After download meta-altera, poky, meta-linaro... I tried to generate the U-Boot image as described in tutorial. But as showed in previous post, it hasn't worked. Note: If Yocto 2.1 (Krogoth) is used paths changes a litlle, but process is the same. I strongly think that U-Boot needs information about the hardware. For example: Default clock frequency in GitHub file pll_config.h is set to 25 MHz, but in my board is 50MHz, and that happens with all the clocks, peripherals, SDRAM timings, etc. In this picture we can see that when MACHINE is set to "cyclone5", default option is board "cyclone5-socdk" https://www.alteraforum.com/forum/attachment.php?attachmentid=12696 So going to board folder we can see some configurations files, these are directly from altera-opensource GitHub (uboot-socfpga tag v2016.09) https://www.alteraforum.com/forum/attachment.php?attachmentid=12697 These ones are files created by Preloader Generator uboot-socfpga v2013.01.01. And contain information about my hardware (so were generated from handoff files...) : https://www.alteraforum.com/forum/attachment.php?attachmentid=12698 Replace files directly doesn't work, I already tried. So finally the question is: which files should i modify to customize u-boot to my hardware? These are some interesting files that contains information about hardware: <u-boot directory in yocto>/board/altera/cyclone5-socdk/qts · iocsr_config.h · pinmux_config.h · pll_config.h · sdram_config.h <u-boot directory in yocto>/include/configs · socfpga_common.h · socfpga_cyclone5_socdk.h <u-boot directory in yocto>/configs · socfpga_cyclone5_defconfig I'm looking forward to any answer! :rolleyes:
Update, there are not a lot of news:Googling I found that there're a script (qts-filter.sh) in Altera SoCfpga U-Boot, that modifies the files generated with Preloader Generator in order to use them in mainline U-Boot. --- Quote Start --- Add script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space. --- Quote End --- http://lists.denx.de/pipermail/u-boot/2015-august/222767.html (http://lists.denx.de/pipermail/u-boot/2015-august/222767.html) Files generated are: <u-boot directory in yocto>/board/altera/cyclone5-socdk/qts · iocsr_config.h · pinmux_config.h · pll_config.h · sdram_config.h Changing the files generated by this script I get an error: "Bad image with mismatched CRC". https://www.alteraforum.com/forum/attachment.php?attachmentid=12699 Do you think should I configure U-Boot with "make config" or should fix mismatched CRC error first? Thank you.
Sorry, I may not be familiar with uboot customization - my impression is that for clock related settings, it should be stored within socfpga_cyclone5_confighttps://rocketboards.org/foswiki/view/documentation/gsrd151compilinglinux (look for the "Building Kernel & U-Boot Separately From Git Trees" section) If I am wrong, then perhaps socfpga_common.h is the correct place :)