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Dual Slave UserLogic

Altera_Forum
Honored Contributor II
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Hi all, 

Can anyone point me in the right direction of an example SOPC peripheral with multiple slave ports? 

I basically want to have a standard slave register port for setting up a continuous stream and another 

slave port that supports streaming so a DMA controller can continuously pull data out of it. 

I can't see any obvious documentation on this and unless I've missed something simple in SOPC I can't 

see how to add the second port as a separate unit, alternatively what changes are required in the hdl to  

support this or won't the userlogic plugin support different modules? 

 

Thanks in advance...
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Altera_Forum
Honored Contributor II
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I suppose I&#39;ll have to dig into the ptf file manually.... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

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Altera_Forum
Honored Contributor II
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I just used two ports. A setup port and data port. I write to the setup port to control (set up) the peripheral and then the data streams into the data port. Never got streaming dma perfect, only 99.99% perfect. Perfect data stream didn&#39;t come until I used a fifo and dma&#39;d those contents on AlmostFull. 

 

I&#39;m about to give streaming dma another try going out to my USB chip though. 

 

Good Luck, 

Ken
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Altera_Forum
Honored Contributor II
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What I did in NiosI was to make two seperate slaves (say 1 and 2). Slave 1 was implemented as a route through for the processor signals. Slave 2 had extra inputs for the processor signals from slave1. 

 

I know it is not the most beatifull solution, but it works perfect. And no hassle with ptf files needed.
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Altera_Forum
Honored Contributor II
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Well I just got stuck in with the Class.ptf for the peripheral and it seems to be okay. 

So one port with control and status signals on it and then a second slave that supports 

streaming transfers (with a 1k fifo inside it for buffering), seems to be okay but i&#39;ll know more 

soon if it can handle my streaming rates.  

It&#39;ll be interesting to see if there is any advantage  

to be gained by using dynamic bus sizing on it since my streamed output is only 12 bits, 

so assuming I promote this to 16 bits, I&#39;m wondering how the dma will handle multi word 

transfers, I&#39;m hoping it will improve throughput by doing a double read and then transfering 

the data. 

 

Thanks anyways, 

...Darren
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Altera_Forum
Honored Contributor II
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Altera is working on an enhanced "New Component" builder which will help you to intantiate multi-port (Slave and/or master). 

I saw it and was very impressed ! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif  

 

Should be available in WW48 with Quartus 4.2. 

 

Maga
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