Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12589 Discussions

EPCS boot loader not copying data correctly

Altera_Forum
Honored Contributor II
945 Views

I am trying to build a Nios project that boots from the EPCS device. 

 

The FPGA code loads correctly, but the instruction data does not. 

 

I am using a Cypress CY7C1021 128kB SRAM for the instruction space. The SRAM starts at address 0x20000 and the Nios exception address is set to 0x20020. The SRAM is configured with 16bit address and 16bit data. 

 

The SRAM works just fine. I can download and execute code from it using the debugger. 

 

However, the EPCS boot loader doesn't load the instruction data correctly into SRAM. 

 

Using the nios2 console, I have examined the SRAM data when the Nios forks to the exception address (0x20020). Is is as follows: 

170> dump 0x20000..+0x100 

00020000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  

00020010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  

00020020 00 00 00 00 00 00 10 10 FF FF 10 10 FD FD 00 00  

00020030 01 01 06 06 00 00 DE DE 00 00 06 06 84 84 D6 D6  

00020040 00 00 00 00 88 88 10 10 00 00 00 00 92 92 18 18  

00020050 03 03 10 10 00 00 10 10 01 01 10 10 FD FD 10 10  

00020060 46 46 00 00 FB FB DE DE 04 04 DF DF 88 88 D8 D8  

00020070 02 02 E0 E0 71 71 00 00 00 00 E0 E0 76 76 00 00  

00020080 00 00 E0 E0 78 78 00 00 01 01 E0 E0 7A 7A 00 00  

00020090 01 01 E0 E0 09 09 D0 D0 00 00 10 10 32 32 10 10  

000200A0 02 02 E0 E0 02 02 E0 E0 88 88 18 18 88 88 10 10  

000200B0 88 88 17 17 00 00 10 10 09 09 D0 D0 1D 1D 10 10  

000200C0 09 09 D1 D1 02 02 E0 E0 88 88 18 18 88 88 10 10  

000200D0 88 88 17 17 00 00 11 11 02 02 E0 E0 88 88 18 18  

000200E0 88 88 10 10 88 88 17 17 09 09 D0 D0 00 00 10 10  

000200F0 20 20 18 18 FF FF 10 10 38 38 20 20 0D 0D 28 28  

171>  

 

This is not correct. You can see that the first instruction is a call to address 0! This causes the EPCS to continously load code to the SRAM. (The EPCS Controller is at address 0x800, which is reached after some fumbling around the address space from 0x0-0x7ff). 

 

If I then proceed to load the code into SRAM using the FS2 console, I can examine the memory and see the correct data: 

172> dump 0x20000..+0x100 

00020000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  

00020010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  

00020020 14 00 81 00 33 00 00 10 04 FF BF 10 16 FD BF 00  

00020030 34 01 C0 06 04 00 C0 DE F4 00 80 06 04 84 A9 D6  

00020040 B4 00 80 00 04 88 89 10 B4 00 C0 00 04 92 C9 18  

00020050 26 03 C0 10 15 00 00 10 04 01 80 10 36 FD FF 10  

00020060 00 46 22 00 04 FB FF DE 15 04 00 DF 3A 88 39 D8  

00020070 45 02 00 E0 C4 71 82 00 0D 00 80 E0 44 76 82 00  

00020080 8D 00 80 E0 C4 78 82 00 0D 01 80 E0 C4 7A 82 00  

00020090 8D 01 80 E0 0B 09 A0 D0 58 00 80 10 1E 32 00 10  

000200A0 05 02 00 E0 03 02 C0 E0 3A 88 05 18 3A 88 C5 10  

000200B0 3A 88 05 17 0B 00 C0 10 8B 09 A0 D0 36 1D C0 10  

000200C0 8B 09 60 D1 03 02 C0 E0 3A 88 05 18 3A 88 C5 10  

000200D0 3A 88 05 17 0B 00 00 11 03 02 C0 E0 3A 88 05 18  

000200E0 3A 88 C5 10 3A 88 05 17 8B 09 E0 D0 0B 00 80 10  

000200F0 3A 20 85 18 CC FF BF 10 3A 38 85 20 1E 0D 80 28  

 

It appears that the EPCS boot loader is copying the data incorrectly, duplicating every other byte. 

 

Anyone have any ideas? 

 

Extra info: 

Quartus II v6.0 SP1 

Nios EDS 6.0 

Cyclone II EP2C20 

EPCS4 

 

Thanks, 

Matt Thomas
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
235 Views

could you tell me how can we read the sram with nios console? 

thx
0 Kudos
Reply