Error (10170): Verilog HDL syntax error at sha256_pipe.v

Nios® V/II Embedded Design Suite (EDS)

Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

Error (10170): Verilog HDL syntax error at sha256_pipe.v

1,135 Views

Hello all,

I got the following error while trying the Verilog HDL. I'm using Quartus II 13.0.

Error (10170): Verilog HDL syntax error at sha256_pipe.v(89) near text "["; expecting "}"

Error (10170): Verilog HDL syntax error at sha256_pipe.v(89) near text "["; expecting "<=", or "="

Here is the code:

data15_p1 <= `S1( SS[i-1].data[`IDX(15)] );

Can anyone assist please, because I am stumped.

Thanks in advance,

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.