Error: BSP component drivers cannot specify mutually independent interrupt APIs

[Benitez__Domingo]

Hi,

I am trying to migrate a golden system reference design (GSRD) for the Terasic DE0-Nano board that is based on a Nios II/e processor to another GSRD for the same board but based on a Nios V/m processor. I have used Quartus Prime Standard Edition 23.1 and Platform Designer for compiling the Nios V/m GSRD design.

I have been able to successfully execute a HelloWorld C program on a DE0-Nano board that was configured with a programming file obtained from compiling the Nios V/m GSRD.

However, I had to modify significantly the Nios II/e GSRD design in two ways:

1.- The SDRAM controller was removed because the IP Library of Platform Designer does not include such a controller. So, I used as main memory the on-chip (FPGA) SRAM memory (8 KB).

2.- Only one interrupt line of the "platform_irq_rx" port of the Nios V/m processor is allowed to be connected to a JTAG_UART controller. If more than one interrupt line were connected to the platform_irq_rx port, the "niosv-bsp -c -t=hal -s=nios_system.sopcinfo settings.bsp" command causes the following error: "BSP component drivers cannot specify mutually independent interrupt APIs. BSP not valid". The BSP was valid only if one interrupt line was connected to the Nios V/m processor. Platform Designer and Quartus compiled the GSRD design successfully when several interrupt lines were connected to the Nios V/m processor.

How could I connect more than one interrupt line to the Nios V/m interrupt controller without this error during the generation of settings.bsp BSP file.

Best regards.

[anchen]

Hi,  

I understand the first interrupt line connected to the Nios V/m processor in your system is from "JTAT UART"? 

For the second interrupt line, from which component in your system?

I wonder the issue is with the component you used in your system, but not the NiosV/m could not connect more interrupt line.

Best Regards,

Ann

[Benitez__Domingo]

Hi,

Thank you very much for your question.

I think the issue is with the component.

When I connect both the JTAG UART and Interval_timer to the platform_irq_rx port of Nios V/m, there is no error during the generation of settings.bsp BSP file.

When the pushbuttons or one of the Expansion_JPx (x=1,2,3,3_in) controllers are connected to Nios V/m interrupt controller, the error is activated during the generation of settings.bsp BSP file.

Attached is the System Contents view of the Platform Designer tool for the GSRD on the DE0-Nano board when the error is produced in the case of only one interrupt line connected to the interrupt controller of Nios V/m.

Best regards

[anchen]

Hi,

The component is “Parallel Port” under University Program and I wonder it is not in good status to support NiosV right now.

I would suggest you to replace them with the "PIO (Parallel I/O) Intel FPGA IP" and try it again to see if the error can be removed.

Best Regards,

Ann

[Benitez__Domingo]

Hi,

The error was removed by replacing the “Parallel Port” under the University Program with the "PIO (Parallel I/O) Intel FPGA IP".

Thank you very much.

It would be nice if the "SDRAM controller IP" were available because the 32 MB of RAM memory available in the DE0-Nano board cannot be used. Anyway, some help to guide me in implementing such a memory controller is welcome.

Best regards,

Domingo

[WZ2]

Hello there,

Thank you for your understanding. Since your question pertains to a different domain compared to previous ones, I suggest opening a new case where domain experts can assist you more effectively. I will go ahead and close the current case.

Thank you once again for your understanding!

Best regards,

WZ