FPGA-HPS Bridge correct bringup and JTAG lockups

[Altera_Forum]

I am getting to grips with this Cyclone V SoC on a Arrow/Terasic SoCKit board, got bare metal C running on it and i continued on to the FPGA bridge features, after 2 days of trying to get it to work i finally figured it out and got it working, but i noticed its very touchy. 

 If you do as much as just have a slight peek at the memory area used by any of the HPS to FPGA bridges before they are set up and running the CPU completely locks up, even looking at there hardware registers causes it. Then once it is all set up and working you can make the chip lock up completely (Not even a system reset can bring it back from this one) if you use the register viewing window in the DS-5 environment to look at the bridge related registers (lwhps2fpgaregs, hps2fpgaregs or fpga2hpsregs) over JTAG. Did notice there is a similar effect when trying to access registers owned by peripherals that are in reset.  How do i make sure when it is safe to touch these memory locations and start using the bridges?  Also is this lockup behavior even normal for the Cyclone V SoC chips? It seams to me like a pretty bad idea to have a whole 1GB of address space turned in to a mine field if the FPGA is not running what its supposed to. It seams to me like doing this should be much less fatal for the CPU (Like simply reading out garbage, falling in to a addressing error trap...or even just rebooting) than just straight out locking up the CPU completely.