FPGA-to-HPS Bridges Design Example

[Altera_Forum]

I am looking at the FPGA-to-HPS Bridges Design Example in Altera website, https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html. I downloaded the project for Cyclone V SoC, and opened the hps_system.qsys, there is a component, AXI Cache Secruity Bridge, I can not find document for this bridge, anyone know what it is for? Thanks......

[Altera_Forum]

Hi, 

 It is a custom IP, you can see the Verilog code given in directory "CV_FPGA_to_HPS_Bridge_Design_Example\ip\axi_cache_secruity_bridge". For more information read the commented lines in .v file and link below. https://www.altera.com/support/support-resources/knowledge-base/embedded/2017/how-do-i-configure-my-soc-system-for-cache-coherent-accesses-fro.html  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)