FPGA-to-HPS SDRAM Bridge in Bare-metal

[Altera_Forum]

FPGA-to-HPS SDRAM Bridge in Bare-metal 

    I am using DE1-SoC to start bare-metal programming for dual-core Cortex-A9 ARM hard processor, Cyclone V.   I'm trying to read data from SDRAM to FPGA using FPGA-to-HPS SDRAM Bridge.   I configured FPGA-to-HPS SDRAM interface in qsys to use avalon-MM Read only, 32 width. I exported FPGA-to-HPS SDRAM Bridge avalon-MM Read only and write verilog state machine for reading ..       always @ (posedge DDR3_clk )  begin  if(sdramState == READ) begin  DDR3_read <=1'b1;  DDR3_write <=1'b0;  if(DDR3_waitrequest==1'b0 && DDR3_read==1'b1)begin  if(!wrfull_vga_fifo ) begin  if(sdram_rd_cnt == (0 + 110591) ) begin  sdram_rd_cnt <= 0;  end else begin  sdram_rd_cnt <= sdram_rd_cnt + 1'b1;  end   DDR3_address <= sdram_rd_cnt; //+ A_FRAME_SA;  data_to_vga <= DDR3_readdata[15:0];  wrreq_vga_fifo <= 1'b1;   end else begin  wrreq_vga_fifo <= 1'b0;  end    end else begin  wrreq_vga_fifo <= 1'b0;   end  end end     And I build preloader using bsp-editor.exe and load it using Eclipes of DS-5.       When I traced FPGA-to-HPS SDRAM Bridge "avalon-MM Read only signals" on signalTab, The output was: avalon_DDR3_waitrequest signal was always 1.   Then I added in main(): alt_bridge_init( ALT_BRIDGE_F2S, NULL, NULL);    The output was:  avalon_DDR3_waitrequest became 0 but still no data read ( avalon_DDR3_readdatavalid was always 0, and avalon_DDR3_readdata was always 0).

[Altera_Forum]

Could this be related to the issue you are seeing?: 

https://www.altera.com/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html?utm_source=altera&utm_medium=newsletter&utm_campaign=facts&utm_content=na_how_can_i_enable_ki_15_08_2016

[Altera_Forum]

Thanks for reply sunshine, 

 It works with me finally. It needs special sequence at operating. 1- Download and run preloader using Eclipes of DS-5, and stop execution at main() by breakpoint . 2- Download .sof file to fpga using quartus programmer. 3- Resume code execution at main() which include 'alt_bridge_init( ALT_BRIDGE_F2S, NULL, NULL); ' instruction. . Then enjoy working FPGA-to-HPS SDRAM Bridge in Bare-metal.

[Altera_Forum]

--- Quote Start ---  Thanks for reply sunshine,  It works with me finally. It needs special sequence at operating. 1- Download and run preloader using Eclipes of DS-5, and stop execution at main() by breakpoint . 2- Download .sof file to fpga using quartus programmer. 3- Resume code execution at main() which include 'alt_bridge_init( ALT_BRIDGE_F2S, NULL, NULL); ' instruction. . Then enjoy working FPGA-to-HPS SDRAM Bridge in Bare-metal.  --- Quote End ---    If I am not mistaken, the GSRD uses the uboot to program the FPGA before the bridge init function took place... perhaps by doing so, it will save some effort (and time) of needing to manually pause at breakpoint, and then program the FPGA using Quartus programmer :)

[Altera_Forum]

Can you send me a basic baremetal example to read HPS SDRAM from FPGA like your VHDL state machine? I spent some weeks of my time and my project don't works. I read all the forum but I think the help of an example could help me now. Please! 

   --- Quote Start ---  FPGA-to-HPS SDRAM Bridge in Bare-metal     I am using DE1-SoC to start bare-metal programming for dual-core Cortex-A9 ARM hard processor, Cyclone V.   I'm trying to read data from SDRAM to FPGA using FPGA-to-HPS SDRAM Bridge.   I configured FPGA-to-HPS SDRAM interface in qsys to use avalon-MM Read only, 32 width. I exported FPGA-to-HPS SDRAM Bridge avalon-MM Read only and write verilog state machine for reading ..       always @ (posedge DDR3_clk )  begin  if(sdramState == READ) begin  DDR3_read <=1'b1;  DDR3_write <=1'b0;  if(DDR3_waitrequest==1'b0 && DDR3_read==1'b1)begin  if(!wrfull_vga_fifo ) begin  if(sdram_rd_cnt == (0 + 110591) ) begin  sdram_rd_cnt <= 0;  end else begin  sdram_rd_cnt <= sdram_rd_cnt + 1'b1;  end   DDR3_address <= sdram_rd_cnt; //+ A_FRAME_SA;  data_to_vga <= DDR3_readdata[15:0];  wrreq_vga_fifo <= 1'b1;   end else begin  wrreq_vga_fifo <= 1'b0;  end    end else begin  wrreq_vga_fifo <= 1'b0;   end  end end     And I build preloader using bsp-editor.exe and load it using Eclipes of DS-5.       When I traced FPGA-to-HPS SDRAM Bridge "avalon-MM Read only signals" on signalTab, The output was: avalon_DDR3_waitrequest signal was always 1.   Then I added in main(): alt_bridge_init( ALT_BRIDGE_F2S, NULL, NULL);    The output was:  avalon_DDR3_waitrequest became 0 but still no data read ( avalon_DDR3_readdatavalid was always 0, and avalon_DDR3_readdata was always 0).  --- Quote End ---  

[Altera_Forum]

Hi, 

This may be what you need. I found it on Altera website... Please see the attachment.  ---------------------------------------------- Custom read and write master templates ----------------------------------------------  This design requires the Quartus II design software 8.0 or later. Each template allows you to easily access the system interconnect fabric using a simple start and acknowledge protocol to control the data movement. To learn more refer to the file "Avalon_MM_Masters_Readme.pdf" available from with the file "exm_avalon_mm_master_templates.zip".  .

[Altera_Forum]

FYI I recommend using the modular SGDMA cores instead of the read and write master templates. The mSGDMA gives a superset of features and it's a standard IP shipped in Qsys. If you want to control the mastering logic with your own logic simply instantiate the read or write master by itself and connect your logic up to the command and response ports. For more information see the documentation here: http://www.alterawiki.com/wiki/modular_sgdma

[Altera_Forum]

Hello all, 

 I have the same problem but unfortunaly I am not as experienced on SOC system to resolve the issue. I'm trying to port a design from a Cyclone 5 (not SOC) to a Cyclone 5 SOC. I'm using a DE1-SOC from Terasic (seems to be a commun dev kit).  My first step is to keep every thing like it is but just changing the DDR3 memory controller to use the HPS one.  So in my qsys system I instanciate the HPS with only the FPGA-to-HPS SDRAM Interface with Avalon-MM and 64 bit width. All the other AXI bridges are set to Unused. For the configuration of the DDR3/SDRAM timing I copy from a kit design example.  Then I try to follow the http://www.alterauserforums.org/forum/showthread.php?t=47099 bare metal example since I only want that the DDR3 be set, FPGA-HPS SDRAM interface be configured. Of course it doesn't work (plus now I have the "Target Message: Could not determine target state" message but that is another problem, I think first I need to know better the design flow)  But I am a bit lost. I don't know if I need to generate the BSP ? I don't have a SD card so no Linux or other complex system. The only thing I know is that I have to make the preloader working since it is on that stage that the HPS configure the pins et interface.  This is the first time I use a HPS, before I used to use the simple nios 2 ^.^.  A lot of design reference use a SD card with Linux....which is too complex system for my application.  The constraint is that I don't want to erase the default bitstream saved in the EPCQ on the developement kit.  If it is possible to have every working on the "temporary memory" will be great. like programming the .sof with signal tap then using eclipse to program the HPS (Like what I used to do with the nios2)  I'm on a debuging process so, don't want at all to save in flash, epcq and to break something that will be difficult to recover....  I will be glad if someone can guide me and show me the way to go.  Thanks in advance.