I was trying to measure the code execution time inside of the Nios II, thus an "interval timer" peripheral could be necessary to do this. Therefore, I recently added an "interval timer" inside of the Nios II system, and this hence lead to some changes upon the corresponding .sopcinfo and .qsys files. The FPGA was compiled successfully, but files in bladerf_nios_bsp were not updated, and I tried to generate a new BSP regarding the changes in Nios II via Nios II Eclipse SBT, but Eclipse showed me an error message:
Error executing 'nios2-bsp-generate-files --bsp-dir . --settings settings.bsp', unexpected return code 1.
SEVERE: nios2-bsp-generate-files failed.
OS of the PC: Windows 11. Software versions: Quartus Prime 17.1 and its built-in Eclipse for Nios II SBT.
Are there anything wrong I did during building the FPGA? Can anyone help? Many thanks in advance.
Can you quick share your design or .sopcinfo I will to replicate from my side.
Did you have a run test previously where it runs OK? Or any design will always turns this error?
Many thanks for your reply.
I encountered this issue just after adding the new module "interval timer" into Nios II system.
The previous design (without adding any new modules) was an existing project and it runs OK. I will upload both .sopcinfo files. The old one is the design without any issues, and the current one is the design which encounters issues.
Please see attached.
Can you tell me more about the interval timer part? Where is it are you adding in Quartus or to you Nios II C code?
Maybe you could share the full "internal timer design" here so I could see the full error and try to see how I could help on it.
Sorry for the confusion, the "interval timer" was renamed by me as a "timestamp_timer" in the design, you may find it from the attached .sopcinfo file, so it was connected as a peripheral in Nios II. At the moment, BSP project has been successfully generated by typing "nios2-bsp-generate-files --bsp-dir . --settings settings.bsp" at the relevant directory via Nios II command shell, but BSP still cannot be automatically generated by clicking "generate BSP" at the sub-menu of "Nios II" in Eclipse.
Hence, generate BSP could be partially resolved at present, as the programme in C can be downlaoded and executed in Nios II. However, some new issues were encountered recently. As I mentioned that I was trying to measure the code running time by using an interval timer (i.e., "timestamp_timer" in my design), but it seems that my programme "froze"/stucked at "alt_timestamp_start()" when executing the code. Please see part of my test code below:
alt_u32 t0, t1;
t0 = alt_timestamp();
t1 = alt_timestamp();
printf("time stamp t0 = %ld \n", t0);
printf("time stamp t1 = %ld \n", t1);
printf("time stamps (t1-t0) = %ld \n", (t1-t0));
In this method, I also enabled timestamp_timer in BSP editor, please see the screen shot below:
Having realised time stamp method may not work properly, I tried another method to measure the code running time, which is almost the same as this one: https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/How-to-calculate-the-time-for-running-the-code-in-Nios-II-and/m-p/1430160 (BTW, the peripheral "interval timer" (i.e., timestamp_timer) connection in my design is exactly the same as the one mentioned in this link). Since both of the methods have to utilise the "interval timer". Hence, I changed my test code as follows:
t = clock();
t = clock() - t;
printf("It took me %ld clocks. \n", t);
Further, in this second method, I enabled sys_clk_timer in BSP editor, since the programme is counting system clock cycles...
However, the second method is returning 0 clocks from printf(), in other words, the value of "t" doesn't change...
There should be something wrong in the design settings (perhaps BSP settings) or something wrong about the timestamp_timer connections. Could you please help to check it? Thank you very much in advance.
I think you sent the old (w/o the interval timer) .sopcinfo file, as I couldn't enable it in the BSP.
Is it possible if you just upload the full archive Quartus design? So I could check the qsys settings as well.
Thanks for the update, glad it worked for you. Maybe you could in your free time to transition to Nios V, you may refer to the Nios V embedded design handbook:
I'm not sure if there are interval timer for Nios V last time I check though, anyway, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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