I have a prototype board that uses a DDR3 SDRAM connected to HPS in Cyclone V device.
The board has a error, bank pins BA and BA are swapped. Is it the way to re-swap this outputs ?
Does your design use both BA & BA? Are both wired up? Or are you intending to use a memory part which doesn't use BA? Dare I suggest that, if they're both wired up and you fit a suitable memory device, it''l just work... Queue barrage of things I've failed to think of. However, having a quick look at the command truth table there aren't any commands that rely on the wiring of BA. So, selecting bank 0 instead of 2 and vice versa should simply result in data being written to and read from different banks in the memory device.
Many thanks for replay. In PCB pin HPS_BA from HPS is connected to pin DDR_BA on DDR3 memory (2 chips of 256Mx16), pin HPS_BA is connected to DDR_BA, pins for address bit  are connected correctly. This error was detected, because of DDR calibration failed during U-boot preloader start.
Datasheet of used memory devices shows that mode registers are selected by BA[1..0] just. I hope there is the way to swap this bits, maybe in u-boot sources, or, I know it's crazy, in HPS system verilog sources.