HPS to FPGA AXI LITE clock crossing brige timeout

[Altera_Forum]

Hello,  

 My Cyclone V SOC HPS AXI-LITE bus is connected to the FPGA fabric with an Avalon MM clock crossing bridge (due to different clock domains).Now, suppose the HPS issues a read request towards the FPGA but it takes the FPGA MANY clock cycles to fetch back the data...  What will happen ? Will the HPS wait as long as it takes for the readdatavalid signal to arrive? Or will it timeout and move into some kind of bus exception / fault mode ?

[Altera_Forum]

The HPS exposes AXI3/Avalon-MM interfaces and not AXI-lite which is an AMBA4 feature. Anyway.... there is no timeout mechanism in the Cyclone/Arria V HPS and the QSYS fabric doesn't have one either unless you build a bridge out of soft logic to perform this. If you created such a bridge you would configure it with a timeout value in clock cycles and monitor the outstanding transactions and the read doesn't return quick enough then you would issue an AXI or Avalon-MM error response back to the HPS. Since there is no timeout mechanism it's important to watch out for reset domains since you wouldn't want to reset the FPGA logic hanging off the HPS and not have the HPS know about that otherwise you'll end up with transactions that do not end.