Hardware vs Software interupt

[Altera_Forum]

Hi there, 

 It doesn't seem clear to me how to specify wether an interupt should be hardware or software. In the Quartus Handbook it does specify "SOPC Builder generates the interrupt controller in one of two configurations, software priority or hardware priority, depending on the interrupt signals present on the master port.". This is great for a component that is created becuase you have the signals required for the system to make hardware interupts. However, if your master is a Nios processor, then you have no control over which signals are beign used and therefore cannot force it to use hardware or software interupts. I assume there must be a setting somewhere that allows youto specify which type of interupt that you require.  Anyone have any advice on this?  Regards Todd

[Altera_Forum]

I haven't read that chapter of the handbook, but perhaps it is refering to software exceptions? (Illegal instruction exceptions, TRAP instructions, etc.)? These are processor-specific things, can generate a software exception. These will be documented in the processor documentation. They are, generally speaking, not generated by events external to the processor. 

 By contrast, hardware interrupts come from peripherals external to the CPU, whether the peripheral is implemented in the FPGA ot not. For example, if you have a slave peripheral, it could generate an interrupt by emitting an irq signal which is connected to Avalon along with the other slave signals. This signal is sent via Avalon (and how you connect that interrupt in SOPC Builder), to the various master peripherals connected to the slave. The behavior and response of each of these masters is dependent on the design of that master; for the Nios II CPU, external interrupts are another exception source (in addition to the software exceptions described above), and they are treated as described in the processor handbook. In addition to the low-level handling of an external interrupt by the CPU, there is typically some software involved that prioritizes incoming interrupts, adjusts the CPU's interrupt enable register bits, and vectors off to interrupt service routines as appropriate... this part is pretty common to how most CPUs operate.  There will be a quiz on Friday covering this lecture........

[Altera_Forum]

I think you may be reading some Nios I documentation and be confused by it. 

 The Nios II interrupt controller does not do any sort of interrupt prioritisation - it presents a mask of which interrupt lines are active and enabled at any particular time. Software must read this mask and decide which function to call.  If you really want to use Nios I instead then sorry for the inconvenience.