Thanks for valuable advice from the forum on selection of RAM for the board.I wish to know.... how the Cyclone starts when powerd on ? Where does it take the code from ??? What is the EPCS device doing ? If i point my .text section to SRAM, does my code physically sit in the SRAM and gets working from there when i power up ? I need these info to design my prototype board. I am not able to get these info in a bunch anywhere !! my exp on FPGAs is jus over a year now. Please help ...
When am running flash programmer in NIOS IDE pointing all the sections to my SRAM what is happening ? is the program written to SRAM or EPCS flash ??When i write the elf and sof using the programmer i am able to re-boot after power off also, how does this happen ? If SRAM is volatile and gets erased on power off, how is it able to work on power on ?
It's basically a two step boot process. In a first step, the FPGA configuration is loaded from EPCS. This also includes initalized internal FPGA RAM (or "ROM"). Configuration load is common to all FPGA applications, with or without soft processor and starts always from EPCS address 0.FPGA applications involving a soft processor have usually stored the processor code and initilized data in the EPCS memory. It's loaded to SRAM in a second boot step under control of the NIOS II IP.
So provided i have a
- large enough EPCS device
- do a flash programming of ELF and SOF file
- my program memory pointing to Onchip/SRAM/Flash etc (Bottleneck will be the speed of the respective devices ??)
Yes Tricky, i understand what you are saying, what i wanted to know is that if i flash my code (sof and elf) using the flash programmer in NIOS IDE, then will the code work every time i power up ?? (PS: i point the reset vector to EPCS and all other the linker script locations to SRAM on the board)