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How to check clk and reset signal when ELF downloading failed?

Altera_Forum
Honored Contributor II
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I learnt from the forum that an ELF downloading failure is likely to be caused by an incorrectly set clk signal or reset signal. The problem is how I can check the clk or reset signal without running the nios program? 

 

My design is a qsys project consisting of nios, some peripherals including external ddr-ram controller and a custom module connected through avalon-mm bus. The system works under a single clock domain generated by the pll that comes with the ddr-ram controller. Reset signal is connected to LOW directly. 

 

Timing requirement was met with some unconstrained paths (input/output ports and paths) which should be fine because previously a similar system ran successfully with these paths unconstrained. Any suggestion will be appreciate.  

 

Thanks guys.
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Altera_Forum
Honored Contributor II
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Hi, 

 

I'm not sure, but may be the problem is the source of your clk. 

I think you should generate a new clk from another pll, for your Nios. 

Don't use the one generated by the pll of the ddr controller. 

 

regards,
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